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* HSD #15012965144: doc: README.socfpga: Add FPGA full reconfiguration flowHEADrel_socfpga_v2022.10_23.05.01_prrel_socfpga_v2022.10_23.04.02_prrel_socfpga_v2022.10_23.04.01_prQPDS23.1_REL_GSRD_PRsocfpga_v2022.10Tien Fong Chee2023-03-201-0/+23
| | | | | | | | Adding required steps of running proper FPGA full reconfiguration. These steps are required to ensure all all outstanding traffic between MPFE to bridge and FPGA to bridge are completed before FPGA configuration. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
* HSD #15012954777-5: arm: socfpga: soc64: Restructure F2S disable functionTien Fong Chee2023-03-201-24/+30
| | | | | | | | Restructure the flow to avoid the bridges being reset twice and with cleaner wait_for_bit status check function. This flow is verified with a lot stress test to ensure validity and reliability in result. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
* HSD #15012954777-4: arm: socfpga: soc64: clean up wait for status codesTien Fong Chee2023-03-201-35/+49
| | | | | | | Replaced both macro set / clear polling functions with single wait_for_bit function for status checking and waiting. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
* HSD #15012954777-3: arm: socfpga: soc64: Clear F2S force drainTien Fong Chee2023-03-201-2/+2
| | | | | | | Wrong register and value were used to clear F2S force drain, so this fix ensure the correct register and value to clear F2S force drain. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
* HSD #15012954777-2: arm: socfpga: soc64: Clear MPFE idle NoC requestTien Fong Chee2023-03-201-2/+2
| | | | | | | Wrong register and value were used to clear MPFE idle NoC request, so this fix ensure the correct register and value to clear MPFE idle NoC request. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
* HSD #15012954777-1: arm: socfpga: soc64: Disable F2S bridgeTien Fong Chee2023-03-201-3/+3
| | | | | | | Wrong register and value were used to disable the F2S bridge, so this fix ensure the correct register and value to disable F2S bridge. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
* HSD #15012971876: ddr: altera: n5x: Fix compilation warningrel_socfpga_v2022.10_23.03.03_prLokanathan, Raaj2023-03-141-26/+26
| | | | | | | | | | | The current n5x has a compilation warning as shown below. This requires to be fixed. "warning: implicit declaration of function reset_type_debug_print" This fixes the compilation warning mentioned above. Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
* HSD #15012857484-2: soc64: configs: Remove CONFIG_SYS_BOOTM_LENLokanathan, Raaj2023-03-102-2/+0
| | | | | | | | | Remove the current CONFIG_SYS_BOOTM_LEN in both agilex-vab and n5x-vab. Previously, the size was set to 32MB, but due to larger kernel image, 64MB size is required. This setting has been set default (64MB) in the Kconfig. Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
* HSD #15012857484-1: soc32: configs: Add CONFIG_SYS_BOOTM_LEN to A10 defconfigLokanathan, Raaj2023-03-102-0/+2
| | | | | | | | Set the CONFIG_SYS_BOOTM_LEN config to both a10-nand and a10-qspi to use 0x2000000 (32MB). The reason this changes is required is due to more memory is required to support larger kernel image. Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
* HSD #14018834576: Set N5X default baudrate to 115200.Lokanathan, Raaj2023-03-081-1/+0
| | | | | | | | | The current baudrate is set at 4800 which causes issue with the uart. N5X default baudrate supposed to be set to 115200. This is being set by default from the Kconfig. In that case, the defined CONFIG_BAUDRATE can be removed from the defconfig. Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
* HSD #14015872909: arch: arm: soc64: Put CPU0 to wait for ATF when only CPU0 ↵Sin Hui Kho2023-03-072-0/+20
| | | | | | | | | | | | | | | | power off/on There is a use case where kernel requested ATF to power off/on only CPU0. However, after ATF power off/on CPU0, CPU0 did not back into the state to wait for ATF. Instead, CPU0 continue to reentry SPL boot sequence because CPU0 is master/primary core. This causing the system reboot from SPL again, while the slave core still in kernel. To resolve this, ATF is set the boot scratch register 8 bit 17 whenever it is a request from kernel to power off/on only CPU0. So, if this boot scratch bit is set, CPU 0 will be able to put into a state to wait for ATF. Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com>
* HSD #14016045851: misc: socfpga_secreg: Fix compilation warningrel_socfpga_v2022.10_23.03.02_prLokanathan, Raaj2023-03-011-1/+1
| | | | | | | | The new code implementation causes some compilation warning which is related to warning: cast to pointer from integer of different size. This is the fix which fixes the warning message during the compilation. Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
* HSD #14016045851: misc: socfpga_secreg: Enable masking supportrel_socfpga_v2022.10_23.03.01_prLokanathan, Raaj2023-02-276-376/+407
| | | | | | | | | Enable masking support in the firewall security register device tree driver. With the masking support, it controls which bits allowed for modification. Only the masking bits set to 1 allows modification. Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
* Remove swbld_releases_2anaraya22023-02-241-7/+0
| | | Remove swbld_releases_2
* env: fat: Fix warning for unused function get_env_filenameKah Jing Lee2023-01-061-0/+2
| | | | | | | Commit <a5091a719e>: Fix warning for unused function get_env_filename when CONFIG_SOCFPGA_RSU_MULTIBOOT is not set. Signed-off-by: Kah Jing Lee <kah.jing.lee@intel.com>
* arch: arm: rsu-spl: Compare FACTORY IMAGE with current running SPL slotKah Jing Lee2023-01-061-1/+2
| | | | | | | | | | | Commit a5091a719e: Bug Fix: Compare FACTORY IMAGE with current running SPL image slot instead of current SSBL slot. Signed-off-by: Kah Jing Lee <kah.jing.lee@intel.com> --- v2: - Rework based on review ---
* arch: arm: rsu: Multiboot selection Uboot SSBL for RSU (MMC)Kah Jing Lee2023-01-065-42/+268
| | | | | | | | | | | | | | | | | | | | | | | | | | Use different Uboot in MMC for each RSU bitstream based on the SPL. Selection is based on the current partition of the running SPL. Based on the SPL partition, multiboot will search for uboot-proper name in MMC to load. E.g: P1 SPL will select u-boot_P1.itb from MMC to load Signed-off-by: Kah Jing Lee <kah.jing.lee@intel.com> --- v2: - Rework based on review - Add the check for FACTORY_IMAGE to only check 15 chars limit for a match (SSBL.FACTORY_IM), since this is the limitation in SPT partition name of 2 bytes --- v3: - Rework based on review - Add a flag to avoid panic triggered when env file is not found in both MMC & QSPI, since current flow allow the env file to find from MMC, QSPI, and NAND --- v4: - Rework based on review ---
* arch: arm: Kconfig: Turn off SOCFPGA_RSU_MULTIBOOT by defaultKah Jing Lee2023-01-061-1/+1
| | | | | | | Turn off SOCFPGA_RSU_MULTIBOOT by default since most users do not use the RSU Multiboot feature by default. Signed-off-by: Kah Jing Lee <kah.jing.lee@intel.com>
* arch: arm: rsu: Multiboot selection Uboot SSBL for RSURadu Bacrau2023-01-066-1/+224
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use different Uboot in QSPI for each RSU bitstream based on the SPL. Selection is based on the naming of SSBL partition, e.g: P1 SPL will select SSBL.P1 for loading the Uboot SSBL. Signed-off-by: Kah Jing Lee <kah.jing.lee@intel.com> Signed-off-by: Radu Bacrau <radu.bacrau@intel.com> --- v2: - Updated on review changes - Add socfpga_rsu_s10_spt_slot to store SSBL address & length - Add Kconfig for RSU multiboot feature - Add CONFIG to build for AGILEX, N5X, S10 --- v3: - Rework based on review - Replace spi_probe with spi_flash_probe_bus_cs - Change error return with linux errno --- v4: - Rework based on review - Update strcpy to strncpy, rename function name --- v5: - Rework based on review - Use strstr to compare the SSBL. prefix instead of the need to strcpy the uboot name before compare - Create get_ssbl_slot function to get both uboot address & size --- v6: - Minor rework, cleanup unused variable and return type --- v7: - Minor rework, cleanup return value and CONFIG for build ---
* arm: socfpga: Add bsp-generator scripts with qts-filterKah Jing Lee2023-01-0610-60/+1986
| | | | | | | | | | | | | | | | | | | | | | | | | HSD#14015480674 & HSD#14015550009: Remove the requirement on the bsp-create-settings script to generate uboot header files. It will process the handoff files from Quartus and convert them to headers usable by U-Boot. Includes the qts filter.sh capability to generate correct format to be used for mainline Uboot on FPGA, namely Cyclone V & Arria V. Usage of each .py scripts: cv_bsp_generator.py : main wrapper to generate uboot required files doc.py : templates for creating documents of generic data model emif.py : parse handoff files to create sdram_config.h hps.py : parse hps.xml to create pinmux_config.h file iocsr.py : process the hiof file from Quartus and generate iocsr .h usable by U-Boot model.py : wrapper for XML DOM parser renderer.py : construction of a specific file format using required data model, in the case, generate the pll_config.h streamer.py : generate license, file header and close tag xmlgrok.py : xml tag navigator Signed-off-by: Kah Jing Lee <kah.jing.lee@intel.com>
* HSD #18025336902: intel: n5x: ddr: update license for secure_vabLokanathan, Raaj2023-01-062-4/+4
| | | | | | | | All the source code of secure_vab.c and secure_vab.h are from Intel. Update the license to use both GPL2.0 and BSD-3 Clause because this copy of code may used for open source and internal project. Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
* HSD #15011830300: ddr: altera: agilex: Update data rate based on HMC rate ↵Sin Hui Kho2022-12-162-2/+23
| | | | | | | | | and RC state Check rate conversion state in HMC from reg_ctrlcfg5 along with the HMC rate in reg_ctrlcfg3 to set the clock/data-rate appropriately. Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com>
* usb: gadget: dfu: Fix the unchecked length fieldVenkatesh Yadav Abbarapu2022-12-141-21/+37
| | | | | | | | | | | | DFU implementation does not bound the length field in USB DFU download setup packets, and it does not verify that the transfer direction. Fixing the length and transfer direction. CVE-2022-2347 Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Reviewed-by: Marek Vasut <marex@denx.de>
* HSD #15011972255: drivers: mtd: spi: Add support for GD55LB02GEBIR SPI NOR flashTeik Heng Chong2022-12-091-0/+5
| | | | | | | Add Support for GigaDevice GD55LB02GEBIR SPI NOR flash as QSPI configuration flash Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com>
* doc: README.socfpga: Update for U-boot 2022.10Lokanathan, Raaj2022-12-071-5/+5
| | | | | | | Update the tested Intel Quartus Software versions and highlight the major changes in this U-boot version. Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
* arm: configs: Clean up the defconfigs for agilex, stratix10, arria10 and cvLokanathan, Raaj2022-12-078-41/+35
| | | | | | | | Previous commits during the uboot 2022.10_RC rebase, the configs were newly added. This causes some test to fail where it cannot boot to uboot SPL. By adding and removing these configs, it fixes the uboot issues. Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
* arm: configs: Set the stack pointer address using CONFIG_CUSTOM_SYS_INIT_SP_ADDRLokanathan, Raaj2022-11-113-0/+6
| | | | | | | Mainline has migrated the CONFIG_SYS_INIT_SP_ADDR config to the Kconfig. However, this config was not added into the non legacy defconfig. Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
* HSD #15011820475: arm: dts: soc64: Revert "changing DDR aliasing addresses"Lokanathan, Raaj2022-11-073-66/+6
| | | | | | | | This commit "HSD #15010938416: arm: dts: soc64: changing DDR aliasing addresses" is causing the uboot to break. Revert this commit fixes the ethernet packet issue. Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
* configs: socfpga: Add missing CONFIG_SYS_MALLOC_F_LEN into socfpga defconfigLokanathan, Raaj2022-11-012-0/+2
| | | | | | | The CONFIG_SYS_MALLOC_F_LEN was missing in the uboot 2022.10. This is required to be added back. Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
* configs: socfpga: Remove outdated configsLokanathan, Raaj2022-11-012-4/+0
| | | | | | Remove some outdated configs from the socfpga defconfigs. Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
* arm: socfpga: Modify the loader script to support changes from mainline.Lokanathan, Raaj2022-11-011-3/+3
| | | | | | | Mainline have made some changes to the loader script where the .uboot_list and .__image_copy_start naming format has been changed. Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
* configs: Remove CONFIG_HW_WATCHDOG from TARGET_SOCFPGA_GEN5Lokanathan, Raaj2022-10-121-1/+0
| | | | | | Mainline, have removed hw_watchdog_reset function and make it to depend on WDT. Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
* drivers: nand: Move the following nand drivers to nand framework objectsLokanathan, Raaj2022-10-121-4/+4
| | | | | | | | | | | | | Move the following nand drivers from NAND_BASE to nand_framework_objects. - nand_amd - nand_hynix - nand_macronix - nand_micron - nand_samsung - nand_toshiba Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
* drivers: fpga: Follow mainline to pass compatible flags to fpga_loadLokanathan, Raaj2022-10-121-1/+2
| | | | | | | Mainline added additional flag to check whether an FPGA driver is able to load a particular FPGA bitstream image. Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
* configs: soc64: Follow mainline to migrate CONFIG_SYS_BOOTM_LEN to KconfigLokanathan, Raaj2022-10-122-5/+0
| | | | | | Mainline have migrated the CONFIG_SYS_BOOTM_LEN to the Kconfig. Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
* configs: socfpga: Follow mainline to add the following configsLokanathan, Raaj2022-10-1211-0/+120
| | | | | | | | | | | | | | | | Mainline uboot added the following configs as per below: - CONFIG_SPL_MAX_SIZE - CONFIG_SPL_HAS_BSS_LINKER_SECTION - CONFIG_SPL_BSS_START_ADDR - CONFIG_SPL_BSS_MAX_SIZE - CONFIG_SPL_STACK - CONFIG_SYS_SPL_MALLOC - CONFIG_HAS_CUSTOM_SPL_MALLOC_START - CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR - CONFIG_SYS_SPL_MALLOC_SIZE Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
* jenkins: Enable PR CI/CDBoon Khai Ng2022-10-111-0/+242
| | | | | | | | Added .jenkins forlder to enable build status check in Pull Request PRcoess. This is just a downstream patch only needed as part of PR Process Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
* doc: README.socfpga: Update for U-boot 2022.07Lokanathan, Raaj2022-10-111-5/+5
| | | | | | | Update the tested Intel Quartus Software versions and highlight the major changes in this U-boot version. Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
* HSD #15011817806: fs-loader: Doc improvementLokanathan, Raaj2022-10-111-0/+8
| | | | | | | Add additional example storage device and partition search for qspi in device tree source Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
* HSD #15011817806: fs-loader: Perform code cleanups on fs-loader driverLokanathan, Raaj2022-10-114-16/+9
| | | | | | | | | The spi_flash_probe() method have removed both the speed and mode configs. Both speed and mode configs are set in spi flash node and spi bus node dts. Hence, both the speed and mode configs are not required to be specified in fs-loader node. Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
* HSD #15011860471: Remove cm_get_qspi_controller_clk_hz from ↵Lokanathan, Raaj2022-10-112-13/+0
| | | | | | | | | | | socfpga_soc64_common.h Mainline have removed cm_get_qspi_controller_clk_hz() and replaced with adding the check-in cadence_qspi.c. During the 2022.07_RC rebase, the mainline changes have been accidentally re-added back. In order to resolve this issue, the qspi controller checks in the socfpga_soc64_common.h needs to be removed. Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
* HSD #15011858928: configs: Set COUNTER_FREQUENCY configurationsLokanathan, Raaj2022-10-116-0/+6
| | | | | | | | Mainline have moved the COUNTER_FREQUENCY config to the Kconfig. In order for the spi refclock to work properly, socfpga configs for agilex and s10-related configs need the COUNTER_FREQUENCY to be added. Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
* HSD #16018042241: arm: dts: arria10: Increase boot partition size for NANDTeoh Ji Sheng2022-10-111-2/+2
| | | | | | | | | Content in NAND boot partition have exceeded 32MB defined in device tree node. Increase boot partition size to 37MB to support larger kernel Image and FPGA bitstream. Signed-off-by: Teoh Ji Sheng <ji.sheng.teoh@intel.com>
* HSD #18019005734: arch: arm: mach-socfpga: SDM Doorbell Issue FixYuslaimi, Alif Zakuan2022-10-111-10/+5
| | | | | | | | This patch clears the buffer overflow check during command buffer write, removes command buffer overflow checking and set to always trigger SDM doorbell at the end of command buffer to ensure SDM can read all of the remaining data. Signed-off-by: Yuslaimi, Alif Zakuan <alif.zakuan.yuslaimi@intel.com>
* HSD #14016953396: rsu: ignore fw cpb errors after fixing cpbsRadu Bacrau2022-10-111-2/+6
| | | | | | | Ignored firmware reported corrupted cpb errors after creating empty cpbs and after restoring cpbs from memory buffer. Signed-off-by: Radu Bacrau <radu.bacrau@intel.com>
* HSD #14016896875: rsu: fix cpb headerRadu Bacrau2022-10-111-1/+1
| | | | | | | Updated the image pointer offset in newly created empty cpbs to be 32 instead of 24, same as for new images. Signed-off-by: Radu Bacrau <radu.bacrau@intel.com>
* HSD #18022972407: drivers: clk: Update comment to describe pll bypassJit Loon Lim2022-10-112-4/+10
| | | | | | | | | Comment about PLL execution when clk init does not match with code implementation. Update comment to describe the PLL execution either is bypass or reset. Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
* HSD #15011744436: configs: socfpga: Remove SPL SPI related configs from CVLokanathan, Raaj2022-10-111-0/+4
| | | | | | | | The Cyclone V has a storage issue as the OCRAM is only 64kb. Due to this reason, the SPL SPI-related configs need to be removed. These configurations are only required during uboot proper only. Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
* spi: Remove speed and mode from spi_flash_probe_bus_csLokanathan, Raaj2022-10-062-4/+0
| | | | | | | | | | The reason for this change is to allow the user to decide whether to use dts, speed and mode or the default value. This is related to the patch below. https://patchwork.ozlabs.org/project/uboot/cover/20220518064648.1843664-1-\ patrice.chotard@foss.st.com/ Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
* test: dm: spi: Replace _spi_get_bus_and_cs() by spi_get_bus_and_cs() in some ↵Patrice Chotard2022-10-061-8/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | case In case _spi_get_bus_and_cs()'s parameters drv_name and dev_name are respectively set to NULL and 0, use spi_get_bus_and_cs() instead. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Marek Behun <marek.behun@nic.cz> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Lukasz Majewski <lukma@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Cc: "Pali Rohár" <pali@kernel.org> Cc: Konstantin Porotchkin <kostap@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Pratyush Yadav <p.yadav@ti.com> Cc: Sean Anderson <seanga2@gmail.com> Cc: Anji J <anji.jagarlmudi@nxp.com> Cc: Biwen Li <biwen.li@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
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