diff options
| author | Lokanathan, Raaj <raaj.lokanathan@intel.com> | 2022-09-01 15:51:33 +0800 |
|---|---|---|
| committer | Lokanathan, Raaj <raaj.lokanathan@intel.com> | 2022-10-11 14:41:49 +0800 |
| commit | c0595cc491e5ec7f385eafacba343ef0d290daf8 (patch) | |
| tree | 3d87fcd3fdb7dea59c8885a20ad54676eb94cb5d | |
| parent | 603e033ee8af5f248a9c07f1634eff9d314ca3e0 (diff) | |
| download | u-boot-socfpga-c0595cc491e5ec7f385eafacba343ef0d290daf8.tar.gz | |
HSD #15011860471: Remove cm_get_qspi_controller_clk_hz from socfpga_soc64_common.h
Mainline have removed cm_get_qspi_controller_clk_hz() and replaced with adding
the check-in cadence_qspi.c. During the 2022.07_RC rebase, the mainline changes
have been accidentally re-added back. In order to resolve this issue, the qspi
controller checks in the socfpga_soc64_common.h needs to be removed.
Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
| -rw-r--r-- | include/configs/socfpga_common.h | 9 | ||||
| -rw-r--r-- | include/configs/socfpga_soc64_common.h | 4 |
2 files changed, 0 insertions, 13 deletions
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 924e1d3c03..dfcb691ed6 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -87,15 +87,6 @@ #endif /* - * QSPI support - */ -/* QSPI reference clock */ -#ifndef __ASSEMBLY__ -unsigned int cm_get_qspi_controller_clk_hz(void); -#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() -#endif - -/* * USB */ diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index b8952fed97..03894dfc22 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -49,10 +49,6 @@ /* * U-Boot environment configurations */ -#ifndef __ASSEMBLY__ -unsigned int cm_get_qspi_controller_clk_hz(void); -#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() -#endif /* * NAND support |