diff options
| author | Sin Hui Kho <sin.hui.kho@intel.com> | 2022-12-02 01:34:53 +0800 |
|---|---|---|
| committer | tienfong <tien.fong.chee@gmail.com> | 2022-12-16 13:54:17 +0800 |
| commit | 9357894a21f4125f14db4e28910b371a4031a818 (patch) | |
| tree | b1393fe5f0579c53334c3d10bef4296ddaa8f7ed | |
| parent | e9e169fc2ee929546316be52b169827d72beda0a (diff) | |
| download | u-boot-socfpga-9357894a21f4125f14db4e28910b371a4031a818.tar.gz | |
HSD #15011830300: ddr: altera: agilex: Update data rate based on HMC rate and RC state
Check rate conversion state in HMC from reg_ctrlcfg5 along with the
HMC rate in reg_ctrlcfg3 to set the clock/data-rate appropriately.
Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com>
| -rw-r--r-- | drivers/ddr/altera/sdram_agilex.c | 20 | ||||
| -rw-r--r-- | drivers/ddr/altera/sdram_soc64.h | 5 |
2 files changed, 23 insertions, 2 deletions
diff --git a/drivers/ddr/altera/sdram_agilex.c b/drivers/ddr/altera/sdram_agilex.c index 9514367c66..0d93eaa2bf 100644 --- a/drivers/ddr/altera/sdram_agilex.c +++ b/drivers/ddr/altera/sdram_agilex.c @@ -77,8 +77,24 @@ int sdram_mmr_init_full(struct udevice *dev) update_value = hmc_readl(plat, NIOSRESERVED0); update_value = (update_value & 0xFF) >> 5; - /* Configure DDR data rate 0-HAlf-rate 1-Quarter-rate */ - update_value |= (hmc_readl(plat, CTRLCFG3) & 0x4); + /* + * Check both HMC rate and RC state + * bit-8 of CTRLCFG5: 1 for rate conversion enabled + * bits[2:0] of CTRLCFG3: 3’b010 – HALF rate. 3’b100 – Quarter rate + * bit-2 of DDRIOCTRL: Configure DDR data rate 0-Half-rate 1-Quarter-rate + */ + u32 ctrlcfg5 = hmc_readl(plat, CTRLCFG5); + u32 ctrlcfg3 = hmc_readl(plat, CTRLCFG3); + + if ((ctrlcfg5 & CTRLCFG5_CFG_CTRL_RC_EN_MASK) || + (ctrlcfg3 & CTRLCFG3_CFG_CTRL_CMD_RATE_QUARTER)) { + /* Quarter-rate */ + update_value |= DDR_HMC_DDRIOCTRL_MPFE_HMCA_DATA_RATE_MSK; + } else { + /* Half-rate */ + update_value &= ~DDR_HMC_DDRIOCTRL_MPFE_HMCA_DATA_RATE_MSK; + } + hmc_ecc_writel(plat, update_value, DDRIOCTRL); /* Copy values MMR IOHMC dramaddrw to HMC adp DRAMADDRWIDTH */ diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index 07a0f9f2ae..a83264174a 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -39,6 +39,7 @@ struct altera_sdram_plat { #define RSTHANDSHAKESTAT 0x218 #define DDR_HMC_DDRIOCTRL_IOSIZE_MSK 0x00000003 +#define DDR_HMC_DDRIOCTRL_MPFE_HMCA_DATA_RATE_MSK BIT(2) #define DDR_HMC_DDRCALSTAT_CAL_MSK BIT(0) #define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK BIT(16) #define DDR_HMC_ECCCTL_CNT_RST_SET_MSK BIT(8) @@ -66,6 +67,7 @@ struct altera_sdram_plat { #define CTRLCFG0 0x28 #define CTRLCFG1 0x2c #define CTRLCFG3 0x34 +#define CTRLCFG5 0x3c #define DRAMTIMING0 0x50 #define CALTIMING0 0x7c #define CALTIMING1 0x80 @@ -79,6 +81,9 @@ struct altera_sdram_plat { #define NIOSRESERVED1 0x114 #define NIOSRESERVED2 0x118 +#define CTRLCFG3_CFG_CTRL_CMD_RATE_QUARTER BIT(2) +#define CTRLCFG5_CFG_CTRL_RC_EN_MASK BIT(8) + #define DRAMADDRW_CFG_COL_ADDR_WIDTH(x) \ (((x) >> 0) & 0x1F) #define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) \ |