diff options
| author | Tien Fong Chee <tien.fong.chee@intel.com> | 2023-02-27 17:27:25 +0800 |
|---|---|---|
| committer | tienfong <tien.fong.chee@gmail.com> | 2023-03-20 11:03:15 +0800 |
| commit | 45a62a422a3db7fcf0636e4ad95e12354e719189 (patch) | |
| tree | f474a40962413cb4acd5c7712d52fa957e566c2c | |
| parent | 775e01b091c58f6d4d6551ef2f194d8b6c0ca8bb (diff) | |
| download | u-boot-socfpga-45a62a422a3db7fcf0636e4ad95e12354e719189.tar.gz | |
HSD #15012954777-3: arm: socfpga: soc64: Clear F2S force drain
Wrong register and value were used to clear F2S force drain, so this
fix ensure the correct register and value to clear F2S force drain.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
| -rw-r--r-- | arch/arm/mach-socfpga/reset_manager_s10.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index c09284e765..577b6e6371 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -154,8 +154,8 @@ static __always_inline void socfpga_f2s_bridges_reset(int enable, POLL_FOR_ZERO((readl(SOCFPGA_F2SDRAM_MGR_ADDRESS + F2SDRAM_SIDEBAND_FLAGINSTATUS0) & flaginstatus_idleack), timeout_ms); - clrbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + - F2SDRAM_SIDEBAND_FLAGOUTSET0, + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTCLR0, flagoutset_fdrain); setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + F2SDRAM_SIDEBAND_FLAGOUTSET0, flagoutset_en); |