diff options
| author | Lokanathan, Raaj <raaj.lokanathan@intel.com> | 2022-09-15 14:34:38 +0800 |
|---|---|---|
| committer | Lokanathan, Raaj <raaj.lokanathan@intel.com> | 2022-11-07 15:59:00 +0800 |
| commit | 40765fb332575bc81e6aa6a72a73d3f2574551ea (patch) | |
| tree | e48d195bd43dac3906e5e57680a3aa13b74e43b6 | |
| parent | 4a2fd51f6a3335e9370cb22f9967527d6ec0532e (diff) | |
| download | u-boot-socfpga-40765fb332575bc81e6aa6a72a73d3f2574551ea.tar.gz | |
HSD #15011820475: arm: dts: soc64: Revert "changing DDR aliasing addresses"
This commit "HSD #15010938416: arm: dts: soc64: changing DDR aliasing addresses"
is causing the uboot to break. Revert this commit fixes the ethernet packet
issue.
Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
| -rw-r--r-- | arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 24 | ||||
| -rwxr-xr-x | arch/arm/dts/socfpga_stratix10_socdk.dts | 24 | ||||
| -rw-r--r-- | arch/arm/dts/socfpga_stratix10_socdk_nand-u-boot.dtsi | 24 |
3 files changed, 6 insertions, 66 deletions
diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi index 8d9a06d587..3664099be5 100644 --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi @@ -28,29 +28,9 @@ }; memory { - /* - * Recommended Aliasing addresses - * - * 16GB - * <0 0x00000000 0 0x80000000>, - * <0x10 0x80000000 3 0x80000000>; - * - * 8GB - * <0 0x00000000 0 0x80000000>, - * <0x10 0x80000000 1 0x80000000>; - * - * 4GB - * <0 0x00000000 0 0x80000000>, - * <0x10 0x80000000 0 0x80000000>; - * - * 2GB - * <0 0x00000000 0 0x80000000>; - * - * Note: Need to set CONFIG_NR_DRAM_BANKS=1 for 2GB in defconfig - * Default CONFIG_NR_DRAM_BANKS=2 is used for other DDR size - */ + /* 8GB */ reg = <0 0x00000000 0 0x80000000>, - <0x10 0x80000000 1 0x80000000>; + <2 0x80000000 1 0x80000000>; }; }; diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index 237461f943..4b5ddc895f 100755 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -36,29 +36,9 @@ #address-cells = <2>; #size-cells = <2>; device_type = "memory"; - /* - * Recommended Aliasing addresses - * - * 16GB - * <0 0x00000000 0 0x80000000>, - * <0x10 0x80000000 3 0x80000000>; - * - * 8GB - * <0 0x00000000 0 0x80000000>, - * <0x10 0x80000000 1 0x80000000>; - * - * 4GB - * <0 0x00000000 0 0x80000000>, - * <0x10 0x80000000 0 0x80000000>; - * - * 2GB - * <0 0x00000000 0 0x80000000>; - * - * Note: Need to set CONFIG_NR_DRAM_BANKS=1 for 2GB in defconfig - * Default CONFIG_NR_DRAM_BANKS=2 is used for other DDR size - */ + /* 4GB */ reg = <0 0x00000000 0 0x80000000>, - <0x10 0x80000000 0 0x80000000>; + <1 0x80000000 0 0x80000000>; u-boot,dm-pre-reloc; }; }; diff --git a/arch/arm/dts/socfpga_stratix10_socdk_nand-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk_nand-u-boot.dtsi index 7797238e7c..597f8baa11 100644 --- a/arch/arm/dts/socfpga_stratix10_socdk_nand-u-boot.dtsi +++ b/arch/arm/dts/socfpga_stratix10_socdk_nand-u-boot.dtsi @@ -12,29 +12,9 @@ #address-cells = <2>; #size-cells = <2>; device_type = "memory"; - /* - * Recommended Aliasing addresses - * - * 16GB - * <0 0x00000000 0 0x80000000>, - * <0x10 0x80000000 3 0x80000000>; - * - * 8GB - * <0 0x00000000 0 0x80000000>, - * <0x10 0x80000000 1 0x80000000>; - * - * 4GB - * <0 0x00000000 0 0x80000000>, - * <0x10 0x80000000 0 0x80000000>; - * - * 2GB - * <0 0x00000000 0 0x80000000>; - * - * Note: Need to set CONFIG_NR_DRAM_BANKS=1 for 2GB in defconfig - * Default CONFIG_NR_DRAM_BANKS=2 is used for other DDR size - */ + /* 4GB */ reg = <0 0x00000000 0 0x80000000>, - <0x10 0x80000000 0 0x80000000>; + <1 0x80000000 0 0x80000000>; u-boot,dm-pre-reloc; }; |