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| author | Lokanathan, Raaj <raaj.lokanathan@intel.com> | 2022-10-05 18:06:54 +0800 |
|---|---|---|
| committer | Lokanathan, Raaj <raaj.lokanathan@intel.com> | 2022-10-12 09:46:08 +0800 |
| commit | 3a69be3d3f528ee418410c171773e39c9b4a449d (patch) | |
| tree | d65215e88f4acf464d672ad710e7e74fbacfd885 | |
| parent | 127c655e355e0e830f2cb2859a6def0fbbc979f0 (diff) | |
| download | u-boot-socfpga-3a69be3d3f528ee418410c171773e39c9b4a449d.tar.gz | |
drivers: fpga: Follow mainline to pass compatible flags to fpga_load
Mainline added additional flag to check whether an FPGA driver is able to
load a particular FPGA bitstream image.
Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
| -rw-r--r-- | drivers/fpga/altera.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index af45da58f4..35eb95544d 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -72,8 +72,9 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, bitstream_type bstype) { int ret_val; + int flags = 0; - ret_val = fpga_load(devnum, (void *)fpgadata, size, bstype); + ret_val = fpga_load(devnum, (void *)fpgadata, size, bstype, flags); /* * Enable the HPS to FPGA bridges when FPGA load is completed |