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| author | Tien Fong Chee <tien.fong.chee@intel.com> | 2023-02-27 17:19:21 +0800 |
|---|---|---|
| committer | tienfong <tien.fong.chee@gmail.com> | 2023-03-20 11:03:15 +0800 |
| commit | e870a2ee57e102de19f9f0283033b3336a54f8a3 (patch) | |
| tree | 42d43b0f963294fc73518485e9949e5756cf5a44 | |
| parent | 2374d01b3122b0734abd14ecaa74c0f510755902 (diff) | |
| download | u-boot-socfpga-e870a2ee57e102de19f9f0283033b3336a54f8a3.tar.gz | |
HSD #15012954777-1: arm: socfpga: soc64: Disable F2S bridge
Wrong register and value were used to disable the F2S bridge, so this fix
ensure the correct register and value to disable F2S bridge.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
| -rw-r--r-- | arch/arm/mach-socfpga/reset_manager_s10.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index c3047cb3fb..246fb4fe21 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * Copyright (C) 2016-2023 Intel Corporation <www.intel.com> * */ @@ -168,8 +168,8 @@ static __always_inline void socfpga_f2s_bridges_reset(int enable, RSTMGR_HDSKREQ_FPGAHSREQ); POLL_FOR_SET(readl(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_HDSKACK), timeout_ms); - clrbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + - F2SDRAM_SIDEBAND_FLAGOUTSET0, flagoutset_en); + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTCLR0, flagoutset_en); __socfpga_udelay(1); setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + F2SDRAM_SIDEBAND_FLAGOUTSET0, |