HSD #14016045851: misc: socfpga_secreg: Enable masking supportrel_socfpga_v2022.10_23.03.01_pr

Enable masking support in the firewall security register
device tree driver. With the masking support, it controls
which bits allowed for modification. Only the masking bits
set to 1 allows modification.

Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>

6 files changed, 407 insertions, 376 deletions

diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
index ca71afa2c1..c30e25729a 100644
--- a/arch/arm/dts/socfpga_agilex-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
@@ -90,10 +90,10 @@
 		reg = <0xf7100200 0x00000014>;
 		intel,offset-settings =
 			/* Disable ocram security at CCU for non secure access */
-			<0x0000004 0x8000ffff>,
-			<0x0000008 0x8000ffff>,
-			<0x000000c 0x8000ffff>,
-			<0x0000010 0x8000ffff>;
+			<0x0000004 0x8000ffff 0xe003ffff>,
+			<0x0000008 0x8000ffff 0xe003ffff>,
+			<0x000000c 0x8000ffff 0xe003ffff>,
+			<0x0000010 0x8000ffff 0xe003ffff>;
 		u-boot,dm-pre-reloc;
 	};
 
@@ -101,9 +101,9 @@
 		reg = <0xf8020000 0x0000001c>;
 		intel,offset-settings =
 			/* Disable MPFE firewall for SMMU */
-			<0x00000000 0x00010101>,
+			<0x00000000 0x00010101 0x00010101>,
 			/* Disable MPFE firewall for HMC adapter */
-			<0x00000004 0x00000001>;
+			<0x00000004 0x00000001 0x00010101>;
 		u-boot,dm-pre-reloc;
 	};
 
@@ -117,25 +117,25 @@
 	soc_noc_fw_ddr_fpga2sdram_inst_0_ddr_scr@f8020100 {
 		reg = <0xf8020100 0x00000050>;
 		intel,offset-settings =
-			<0x0000000 0x00000000>,
-			<0x0000004 0x00000000>,
-			<0x0000008 0x00000000>,
-			<0x0000010 0x00000000>,
-			<0x0000014 0x00000000>,
-			<0x0000018 0x0000ffff>,
-			<0x000001c 0x00000000>,
-			<0x0000020 0x00000000>,
-			<0x0000024 0x00000000>,
-			<0x0000028 0x0000ffff>,
-			<0x000002c 0x00000000>,
-			<0x0000030 0x00000000>,
-			<0x0000034 0x00000000>,
-			<0x0000038 0x0000ffff>,
-			<0x000003c 0x00000000>,
-			<0x0000040 0x00000000>,
-			<0x0000044 0x00000000>,
-			<0x0000048 0x0000ffff>,
-			<0x000004c 0x00000000>;
+			<0x0000000 0x00000000 0x0000000f>,
+			<0x0000004 0x00000000 0x0000000f>,
+			<0x0000008 0x00000000 0x0000000f>,
+			<0x0000010 0x00000000 0xffff0000>,
+			<0x0000014 0x00000000 0x000000ff>,
+			<0x0000018 0x00000000 0xffff0000>,
+			<0x000001c 0x00000000 0x000000ff>,
+			<0x0000020 0x00000000 0xffff0000>,
+			<0x0000024 0x00000000 0x000000ff>,
+			<0x0000028 0x00000000 0xffff0000>,
+			<0x000002c 0x00000000 0x000000ff>,
+			<0x0000030 0x00000000 0xffff0000>,
+			<0x0000034 0x00000000 0x000000ff>,
+			<0x0000038 0x00000000 0xffff0000>,
+			<0x000003c 0x00000000 0x000000ff>,
+			<0x0000040 0x00000000 0xffff0000>,
+			<0x0000044 0x00000000 0x000000ff>,
+			<0x0000048 0x00000000 0xffff0000>,
+			<0x000004c 0x00000000 0x000000ff>;
 		u-boot,dm-pre-reloc;
 	};
 
@@ -149,11 +149,11 @@
 	soc_mpfe_noc_inst_0_ccu_mem0_I_main_QosGenerator@f8022080 {
 		reg = <0xf8022080 0x0000001c>;
 		intel,offset-settings =
-			<0x0000008 0x80000200>,
-			<0x000000c 0x00000003>,
-			<0x0000010 0x00000BFE>,
-			<0x0000014 0x00000008>,
-			<0x0000018 0x00000000>;
+			<0x0000008 0x00000200 0x00000303>,
+			<0x000000c 0x00000003 0x00000003>,
+			<0x0000010 0x00000BFE 0x00007fff>,
+			<0x0000014 0x00000008 0x000003ff>,
+			<0x0000018 0x00000000 0x0000000f>;
 		u-boot,dm-pre-reloc;
 	};
 };
diff --git a/arch/arm/dts/socfpga_n5x-u-boot.dtsi b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
index 65d874a5a1..d7d4262427 100644
--- a/arch/arm/dts/socfpga_n5x-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
@@ -139,10 +139,10 @@
 		reg = <0xf7100200 0x00000014>;
 		intel,offset-settings =
 			/* Disable ocram security at CCU for non secure access */
-			<0x0000004 0x8000ffff>,
-			<0x0000008 0x8000ffff>,
-			<0x000000c 0x8000ffff>,
-			<0x0000010 0x8000ffff>;
+			<0x0000004 0x8000ffff 0xe007ffff>,
+			<0x0000008 0x8000ffff 0xe007ffff>,
+			<0x000000c 0x8000ffff 0xe007ffff>,
+			<0x0000010 0x8000ffff 0xe007ffff>;
 		u-boot,dm-pre-reloc;
 	};
 
@@ -150,9 +150,9 @@
 		reg = <0xf8020000 0x0000001c>;
 		intel,offset-settings =
 			/* Disable MPFE firewall for SMMU */
-			<0x00000000 0x00010101>,
+			<0x00000000 0x00010101 0x00010101>,
 			/* Disable MPFE firewall for HMC adapter */
-			<0x00000004 0x00000001>;
+			<0x00000004 0x00000001 0x00010101>;
 		u-boot,dm-pre-reloc;
 	};
 };
diff --git a/arch/arm/dts/socfpga_soc64_u-boot.dtsi b/arch/arm/dts/socfpga_soc64_u-boot.dtsi
index 851fde536c..56865a0639 100644
--- a/arch/arm/dts/socfpga_soc64_u-boot.dtsi
+++ b/arch/arm/dts/socfpga_soc64_u-boot.dtsi
@@ -17,9 +17,9 @@
 				reg = <0xffd12000 0x00000230>;
 				intel,offset-settings =
 					/* Enable non-secure interface to DMA */
-					<0x00000020 0xff010000>,
+					<0x00000020 0xff010000 0xff010011>,
 					/* Enable non-secure interface to DMA periph */
-					<0x00000024 0xffffffff>;
+					<0x00000024 0xffffffff 0xffffffff>;
 				u-boot,dm-pre-reloc;
 			};
 
@@ -27,29 +27,29 @@
 				reg = <0xffd21000 0x00000074>;
 				intel,offset-settings =
 					/* Disable L4 periphs firewall */
-					<0x00000000 0x01010001>,
-					<0x00000004 0x01010001>,
-					<0x0000000c 0x01010001>,
-					<0x00000010 0x01010001>,
-					<0x0000001c 0x01010001>,
-					<0x00000020 0x01010001>,
-					<0x00000024 0x01010001>,
-					<0x00000028 0x01010001>,
-					<0x0000002c 0x01010001>,
-					<0x00000030 0x01010001>,
-					<0x00000034 0x01010001>,
-					<0x00000040 0x01010001>,
-					<0x00000044 0x01010001>,
-					<0x00000048 0x01010001>,
-					<0x00000050 0x01010001>,
-					<0x00000054 0x01010001>,
-					<0x00000058 0x01010001>,
-					<0x0000005c 0x01010001>,
-					<0x00000060 0x01010001>,
-					<0x00000064 0x01010001>,
-					<0x00000068 0x01010001>,
-					<0x0000006c 0x01010001>,
-					<0x00000070 0x01010001>;
+					<0x00000000 0x01010001 0x01010001>,
+					<0x00000004 0x01010001 0x01010001>,
+					<0x0000000c 0x01010001 0x01010001>,
+					<0x00000010 0x01010001 0x01010001>,
+					<0x0000001c 0x01010001 0x01010101>,
+					<0x00000020 0x01010001 0x01010101>,
+					<0x00000024 0x01010001 0x01010101>,
+					<0x00000028 0x01010001 0x01010101>,
+					<0x0000002c 0x01010001 0x01010001>,
+					<0x00000030 0x01010001 0x01010001>,
+					<0x00000034 0x01010001 0x01010001>,
+					<0x00000040 0x01010001 0x01010001>,
+					<0x00000044 0x01010001 0x01010101>,
+					<0x00000048 0x01010001 0x01010101>,
+					<0x00000050 0x01010001 0x01010101>,
+					<0x00000054 0x01010001 0x01010101>,
+					<0x00000058 0x01010001 0x01010101>,
+					<0x0000005c 0x01010001 0x01010101>,
+					<0x00000060 0x01010001 0x01010101>,
+					<0x00000064 0x01010001 0x01010101>,
+					<0x00000068 0x01010001 0x01010101>,
+					<0x0000006c 0x01010001 0x01010101>,
+					<0x00000070 0x01010001 0x01010101>;
 				u-boot,dm-pre-reloc;
 			};
 
@@ -57,54 +57,54 @@
 				reg = <0xffd21100 0x00000098>;
 				intel,offset-settings =
 					/* Disable L4 system firewall */
-					<0x00000008 0x01010001>,
-					<0x0000000c 0x01010001>,
-					<0x00000010 0x01010001>,
-					<0x00000014 0x01010001>,
-					<0x00000018 0x01010001>,
-					<0x0000001c 0x01010001>,
-					<0x00000020 0x01010001>,
-					<0x0000002c 0x01010001>,
-					<0x00000030 0x01010001>,
-					<0x00000034 0x01010001>,
-					<0x00000038 0x01010001>,
-					<0x00000040 0x01010001>,
-					<0x00000044 0x01010001>,
-					<0x00000048 0x01010001>,
-					<0x0000004c 0x01010001>,
-					<0x00000054 0x01010001>,
-					<0x00000058 0x01010001>,
-					<0x0000005c 0x01010001>,
-					<0x00000060 0x01010001>,
-					<0x00000064 0x01010001>,
-					<0x00000068 0x01010001>,
-					<0x0000006c 0x01010001>,
-					<0x00000070 0x01010001>,
-					<0x00000074 0x01010001>,
-					<0x00000078 0x01010001>,
-					<0x00000090 0x01010001>,
-					<0x00000094 0x01010001>;
+					<0x00000008 0x01010001 0x01010001>,
+					<0x0000000c 0x01010001 0x01010001>,
+					<0x00000010 0x01010001 0x01010001>,
+					<0x00000014 0x01010001 0x01010001>,
+					<0x00000018 0x01010001 0x01010001>,
+					<0x0000001c 0x01010001 0x01010001>,
+					<0x00000020 0x01010001 0x01010001>,
+					<0x0000002c 0x01010001 0x01010001>,
+					<0x00000030 0x01010001 0x01010001>,
+					<0x00000034 0x01010001 0x01010001>,
+					<0x00000038 0x01010001 0x01010001>,
+					<0x00000040 0x01010001 0x01010001>,
+					<0x00000044 0x01010001 0x01010001>,
+					<0x00000048 0x01010001 0x01010001>,
+					<0x0000004c 0x01010001 0x01010001>,
+					<0x00000054 0x01010001 0x01010001>,
+					<0x00000058 0x01010001 0x01010001>,
+					<0x0000005c 0x01010001 0x01010001>,
+					<0x00000060 0x01010001 0x01010101>,
+					<0x00000064 0x01010001 0x01010101>,
+					<0x00000068 0x01010001 0x01010101>,
+					<0x0000006c 0x01010001 0x01010101>,
+					<0x00000070 0x01010001 0x01010101>,
+					<0x00000074 0x01010001 0x01010101>,
+					<0x00000078 0x01010001 0x03010001>,
+					<0x00000090 0x01010001 0x01010001>,
+					<0x00000094 0x01010001 0x01010001>;
 				u-boot,dm-pre-reloc;
 			};
 
 			noc_fw_soc2fpga_soc2fpga_scr@ffd21200 {
 				reg = <0xffd21200 0x00000004>;
 				/* Disable soc2fpga security access */
-				intel,offset-settings = <0x00000000 0x0ffe0101>;
+				intel,offset-settings = <0x00000000 0x0ffe0101 0x0ffe0101>;
 				u-boot,dm-pre-reloc;
 			};
 
 			noc_fw_lwsoc2fpga_lwsoc2fpga_scr@ffd21300 {
 				reg = <0xffd21300 0x00000004>;
 				/* Disable lightweight soc2fpga security access */
-				intel,offset-settings = <0x00000000 0x0ffe0101>;
+				intel,offset-settings = <0x00000000 0x0ffe0101 0x0ffe0101>;
 				u-boot,dm-pre-reloc;
 			};
 
 			noc_fw_tcu_tcu_scr@ffd21400 {
 				reg = <0xffd21400 0x00000004>;
 				/* Disable DMA ECC security access, for SMMU use */
-				intel,offset-settings = <0x00000000 0x01010001>;
+				intel,offset-settings = <0x00000000 0x01010001 0x01010001>;
 				u-boot,dm-pre-reloc;
 			};
 
@@ -112,7 +112,7 @@
 				reg = <0xffd24800 0x0000000c>;
 				intel,offset-settings =
 					/* Enable non-prviledged access to various periphs */
-					<0x00000000 0xfff73ffb>;
+					<0x00000000 0xfff73ffb 0xfff73ffb>;
 				u-boot,dm-pre-reloc;
 			};
 		};
diff --git a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
index ed844c0080..c0d41cdd3c 100644
--- a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
@@ -13,43 +13,43 @@
 		reg = <0xf7000000 0x00049e60>;
 		intel,offset-settings =
 			/* Enable access to DDR reg from CPU */
-			<0x0004400 0xF8000000>,
+			<0x0004400 0xF8000000 0xffffffff>,
 
 			/* Enable access to DDR region from CPU */
-			<0x00045c0 0x00000000>,
-			<0x00045e0 0x00000000>,
-			<0x0004600 0x00000000>,
-			<0x0004620 0x00000000>,
-			<0x0004640 0x00000000>,
-			<0x0004660 0x00000000>,
+			<0x00045c0 0x00000000 0xffffffdf>,
+			<0x00045e0 0x00000000 0xffffffdf>,
+			<0x0004600 0x00000000 0xffffffdf>,
+			<0x0004620 0x00000000 0xffffffdf>,
+			<0x0004640 0x00000000 0xffffffdf>,
+			<0x0004660 0x00000000 0xffffffdf>,
 
 			/* Disable ocram security at CCU for non secure access */
-			<0x0004688 0xfffc0000>,
-			<0x0018628 0xfffc0000>,
+			<0x0004688 0xfffc0000 0xffffffcf>,
+			<0x0018628 0xfffc0000 0xffffffcf>,
 
 			/* Enable access to DDR region from IO master */
-			<0x00018560 0x00000000>,
-			<0x00018580 0x00000000>,
-			<0x000185a0 0x00000000>,
-			<0x000185c0 0x00000000>,
-			<0x000185e0 0x00000000>,
-			<0x00018600 0x00000000>,
+			<0x00018560 0x00000000 0xffffffdf>,
+			<0x00018580 0x00000000 0xffffffdf>,
+			<0x000185a0 0x00000000 0xffffffdf>,
+			<0x000185c0 0x00000000 0xffffffdf>,
+			<0x000185e0 0x00000000 0xffffffdf>,
+			<0x00018600 0x00000000 0xffffffdf>,
 
 			/* Enable access to DDR region from TCU */
-			<0x0002c520 0x00000000>,
-			<0x0002c540 0x00000000>,
-			<0x0002c560 0x00000000>,
-			<0x0002c580 0x00000000>,
-			<0x0002c5a0 0x00000000>,
-			<0x0002c5c0 0x00000000>,
+			<0x0002c520 0x00000000 0xffffffdf>,
+			<0x0002c540 0x00000000 0xffffffdf>,
+			<0x0002c560 0x00000000 0xffffffdf>,
+			<0x0002c580 0x00000000 0xffffffdf>,
+			<0x0002c5a0 0x00000000 0xffffffdf>,
+			<0x0002c5c0 0x00000000 0xffffffdf>,
 
 			/* Enable access to DDR region from FPGA */
-			<0x000105a0 0x00000000>,
-			<0x000105c0 0x00000000>,
-			<0x000105e0 0x00000000>,
-			<0x00010600 0x00000000>,
-			<0x00010620 0x00000000>,
-			<0x00010640 0x00000000>;
+			<0x000105a0 0x00000000 0xffffffdf>,
+			<0x000105c0 0x00000000 0xffffffdf>,
+			<0x000105e0 0x00000000 0xffffffdf>,
+			<0x00010600 0x00000000 0xffffffdf>,
+			<0x00010620 0x00000000 0xffffffdf>,
+			<0x00010640 0x00000000 0xffffffdf>;
 		u-boot,dm-pre-reloc;
 	};
 
@@ -65,75 +65,75 @@
 	soc_noc_fw_ddr_fpga2sdram_inst_0_ddr_scr@f8020200 {
 		reg = <0xf8020200 0x00000050>;
 		intel,offset-settings =
-			<0x0000000 0x00000000>,
-			<0x0000004 0x00000000>,
-			<0x0000008 0x00000000>,
-			<0x0000010 0x00000000>,
-			<0x0000014 0x00000000>,
-			<0x0000018 0x0000ffff>,
-			<0x000001c 0x00000000>,
-			<0x0000020 0x00000000>,
-			<0x0000024 0x00000000>,
-			<0x0000028 0x0000ffff>,
-			<0x000002c 0x00000000>,
-			<0x0000030 0x00000000>,
-			<0x0000034 0x00000000>,
-			<0x0000038 0x0000ffff>,
-			<0x000003c 0x00000000>,
-			<0x0000040 0x00000000>,
-			<0x0000044 0x00000000>,
-			<0x0000048 0x0000ffff>,
-			<0x000004c 0x00000000>;
+			<0x0000000 0x00000000 0x0000000f>,
+			<0x0000004 0x00000000 0x0000000f>,
+			<0x0000008 0x00000000 0x0000000f>,
+			<0x0000010 0x00000000 0xffff0000>,
+			<0x0000014 0x00000000 0x0000001f>,
+			<0x0000018 0x00000000 0xffff0000>,
+			<0x000001c 0x00000000 0x0000001f>,
+			<0x0000020 0x00000000 0xffff0000>,
+			<0x0000024 0x00000000 0x0000001f>,
+			<0x0000028 0x00000000 0xffff0000>,
+			<0x000002c 0x00000000 0x0000001f>,
+			<0x0000030 0x00000000 0xffff0000>,
+			<0x0000034 0x00000000 0x0000001f>,
+			<0x0000038 0x00000000 0xffff0000>,
+			<0x000003c 0x00000000 0x0000001f>,
+			<0x0000040 0x00000000 0xffff0000>,
+			<0x0000044 0x00000000 0x0000001f>,
+			<0x0000048 0x00000000 0xffff0000>,
+			<0x000004c 0x00000000 0x0000001f>;
 		u-boot,dm-pre-reloc;
 	};
 
 	soc_noc_fw_ddr_fpga2sdram_inst_1_ddr_scr@f8020300 {
 		reg = <0xf8020300 0x00000050>;
 		intel,offset-settings =
-			<0x0000000 0x00000000>,
-			<0x0000004 0x00000000>,
-			<0x0000008 0x00000000>,
-			<0x0000010 0x00000000>,
-			<0x0000014 0x00000000>,
-			<0x0000018 0x0000ffff>,
-			<0x000001c 0x00000000>,
-			<0x0000020 0x00000000>,
-			<0x0000024 0x00000000>,
-			<0x0000028 0x0000ffff>,
-			<0x000002c 0x00000000>,
-			<0x0000030 0x00000000>,
-			<0x0000034 0x00000000>,
-			<0x0000038 0x0000ffff>,
-			<0x000003c 0x00000000>,
-			<0x0000040 0x00000000>,
-			<0x0000044 0x00000000>,
-			<0x0000048 0x0000ffff>,
-			<0x000004c 0x00000000>;
+			<0x0000000 0x00000000 0x0000000f>,
+			<0x0000004 0x00000000 0x0000000f>,
+			<0x0000008 0x00000000 0x0000000f>,
+			<0x0000010 0x00000000 0xffff0000>,
+			<0x0000014 0x00000000 0x0000001f>,
+			<0x0000018 0x00000000 0xffff0000>,
+			<0x000001c 0x00000000 0x0000001f>,
+			<0x0000020 0x00000000 0xffff0000>,
+			<0x0000024 0x00000000 0x0000001f>,
+			<0x0000028 0x00000000 0xffff0000>,
+			<0x000002c 0x00000000 0x0000001f>,
+			<0x0000030 0x00000000 0xffff0000>,
+			<0x0000034 0x00000000 0x0000001f>,
+			<0x0000038 0x00000000 0xffff0000>,
+			<0x000003c 0x00000000 0x0000001f>,
+			<0x0000040 0x00000000 0xffff0000>,
+			<0x0000044 0x00000000 0x0000001f>,
+			<0x0000048 0x00000000 0xffff0000>,
+			<0x000004c 0x00000000 0x0000001f>;
 		u-boot,dm-pre-reloc;
 	};
 
 	soc_noc_fw_ddr_fpga2sdram_inst_2_ddr_scr@f8020400 {
 		reg = <0xf8020400 0x00000050>;
 		intel,offset-settings =
-			<0x0000000 0x00000000>,
-			<0x0000004 0x00000000>,
-			<0x0000008 0x00000000>,
-			<0x0000010 0x00000000>,
-			<0x0000014 0x00000000>,
-			<0x0000018 0x0000ffff>,
-			<0x000001c 0x00000000>,
-			<0x0000020 0x00000000>,
-			<0x0000024 0x00000000>,
-			<0x0000028 0x0000ffff>,
-			<0x000002c 0x00000000>,
-			<0x0000030 0x00000000>,
-			<0x0000034 0x00000000>,
-			<0x0000038 0x0000ffff>,
-			<0x000003c 0x00000000>,
-			<0x0000040 0x00000000>,
-			<0x0000044 0x00000000>,
-			<0x0000048 0x0000ffff>,
-			<0x000004c 0x00000000>;
+			<0x0000000 0x00000000 0x0000000f>,
+			<0x0000004 0x00000000 0x0000000f>,
+			<0x0000008 0x00000000 0x0000000f>,
+			<0x0000010 0x00000000 0xffff0000>,
+			<0x0000014 0x00000000 0x0000001f>,
+			<0x0000018 0x00000000 0xffff0000>,
+			<0x000001c 0x00000000 0x0000001f>,
+			<0x0000020 0x00000000 0xffff0000>,
+			<0x0000024 0x00000000 0x0000001f>,
+			<0x0000028 0x00000000 0xffff0000>,
+			<0x000002c 0x00000000 0x0000001f>,
+			<0x0000030 0x00000000 0xffff0000>,
+			<0x0000034 0x00000000 0x0000001f>,
+			<0x0000038 0x00000000 0xffff0000>,
+			<0x000003c 0x00000000 0x0000001f>,
+			<0x0000040 0x00000000 0xffff0000>,
+			<0x0000044 0x00000000 0x0000001f>,
+			<0x0000048 0x00000000 0xffff0000>,
+			<0x000004c 0x00000000 0x0000001f>;
 		u-boot,dm-pre-reloc;
 	};
 
@@ -147,11 +147,11 @@
 	soc_ddr_scheduler_inst_0_ccu_mem0_I_main_QosGenerator@f8022080 {
 		reg = <0xf8022080 0x0000001c>;
 		intel,offset-settings =
-			<0x0000008 0x80000000>,
-			<0x000000c 0x00000001>,
-			<0x0000010 0x00000BFE>,
-			<0x0000014 0x00000008>,
-			<0x0000018 0x00000000>;
+			<0x0000008 0x00000000 0x00000303>,
+			<0x000000c 0x00000001 0x00000003>,
+			<0x0000010 0x00000BFE 0x00001fff>,
+			<0x0000014 0x00000008 0x000003ff>,
+			<0x0000018 0x00000000 0x00000007>;
 		u-boot,dm-pre-reloc;
 	};
 };
diff --git a/doc/device-tree-bindings/misc/socfpga_secreg.txt b/doc/device-tree-bindings/misc/socfpga_secreg.txt
index a6f4f22edf..97640b74d9 100644
--- a/doc/device-tree-bindings/misc/socfpga_secreg.txt
+++ b/doc/device-tree-bindings/misc/socfpga_secreg.txt
@@ -5,8 +5,10 @@ Required properties:
 
 - compatible: should contain "intel,socfpga-secreg"
 - reg: Physical base address and size of block register.
-- intel,offset-settings: 32-bit offset address of block register, and then
-                         followed by 32-bit value settings.
+- intel,offset-settings: 32-bit offset address of block register,
+			 followed by 32-bit value settings and
+			 the masking bits, only masking bit
+			 set to 1 allows modification.
 
 The device tree node which describes secure and privilege register access
 configuration in compile time.
@@ -41,9 +43,9 @@ Path: arch/arm/dts/socfpga_soc64_u-boot.dtsi
 			reg = <0xffd12000 0x00000230>;
 			intel,offset-settings =
 				/* Enable non-secure interface to DMA */
-				<0x00000020 0xff010000>,
+				<0x00000020 0xff010000 0xff010011>,
 				/* Enable non-secure interface to DMA periph */
-				<0x00000024 0xffffffff>;
+				<0x00000024 0xffffffff 0xffffffff>;
 			u-boot,dm-pre-reloc;
 		};
 
@@ -51,29 +53,29 @@ Path: arch/arm/dts/socfpga_soc64_u-boot.dtsi
 			reg = <0xffd21000 0x00000074>;
 			intel,offset-settings =
 				/* Disable L4 periphs firewall */
-				<0x00000000 0x01010001>,
-				<0x00000004 0x01010001>,
-				<0x0000000c 0x01010001>,
-				<0x00000010 0x01010001>,
-				<0x0000001c 0x01010001>,
-				<0x00000020 0x01010001>,
-				<0x00000024 0x01010001>,
-				<0x00000028 0x01010001>,
-				<0x0000002c 0x01010001>,
-				<0x00000030 0x01010001>,
-				<0x00000034 0x01010001>,
-				<0x00000040 0x01010001>,
-				<0x00000044 0x01010001>,
-				<0x00000048 0x01010001>,
-				<0x00000050 0x01010001>,
-				<0x00000054 0x01010001>,
-				<0x00000058 0x01010001>,
-				<0x0000005c 0x01010001>,
-				<0x00000060 0x01010001>,
-				<0x00000064 0x01010001>,
-				<0x00000068 0x01010001>,
-				<0x0000006c 0x01010001>,
-				<0x00000070 0x01010001>;
+				<0x00000000 0x01010001 0x01010001>,
+				<0x00000004 0x01010001 0x01010001>,
+				<0x0000000c 0x01010001 0x01010001>,
+				<0x00000010 0x01010001 0x01010001>,
+				<0x0000001c 0x01010001 0x01010101>,
+				<0x00000020 0x01010001 0x01010101>,
+				<0x00000024 0x01010001 0x01010101>,
+				<0x00000028 0x01010001 0x01010101>,
+				<0x0000002c 0x01010001 0x01010001>,
+				<0x00000030 0x01010001 0x01010001>,
+				<0x00000034 0x01010001 0x01010001>,
+				<0x00000040 0x01010001 0x01010001>,
+				<0x00000044 0x01010001 0x01010101>,
+				<0x00000048 0x01010001 0x01010101>,
+				<0x00000050 0x01010001 0x01010101>,
+				<0x00000054 0x01010001 0x01010101>,
+				<0x00000058 0x01010001 0x01010101>,
+				<0x0000005c 0x01010001 0x01010101>,
+				<0x00000060 0x01010001 0x01010101>,
+				<0x00000064 0x01010001 0x01010101>,
+				<0x00000068 0x01010001 0x01010101>,
+				<0x0000006c 0x01010001 0x01010101>,
+				<0x00000070 0x01010001 0x01010101>;
 			u-boot,dm-pre-reloc;
 		};
 
@@ -81,54 +83,54 @@ Path: arch/arm/dts/socfpga_soc64_u-boot.dtsi
 			reg = <0xffd21100 0x00000098>;
 			intel,offset-settings =
 				/* Disable L4 system firewall */
-				<0x00000008 0x01010001>,
-				<0x0000000c 0x01010001>,
-				<0x00000010 0x01010001>,
-				<0x00000014 0x01010001>,
-				<0x00000018 0x01010001>,
-				<0x0000001c 0x01010001>,
-				<0x00000020 0x01010001>,
-				<0x0000002c 0x01010001>,
-				<0x00000030 0x01010001>,
-				<0x00000034 0x01010001>,
-				<0x00000038 0x01010001>,
-				<0x00000040 0x01010001>,
-				<0x00000044 0x01010001>,
-				<0x00000048 0x01010001>,
-				<0x0000004c 0x01010001>,
-				<0x00000054 0x01010001>,
-				<0x00000058 0x01010001>,
-				<0x0000005c 0x01010001>,
-				<0x00000060 0x01010001>,
-				<0x00000064 0x01010001>,
-				<0x00000068 0x01010001>,
-				<0x0000006c 0x01010001>,
-				<0x00000070 0x01010001>,
-				<0x00000074 0x01010001>,
-				<0x00000078 0x01010001>,
-				<0x00000090 0x01010001>,
-				<0x00000094 0x01010001>;
+				<0x00000008 0x01010001 0x01010001>,
+				<0x0000000c 0x01010001 0x01010001>,
+				<0x00000010 0x01010001 0x01010001>,
+				<0x00000014 0x01010001 0x01010001>,
+				<0x00000018 0x01010001 0x01010001>,
+				<0x0000001c 0x01010001 0x01010001>,
+				<0x00000020 0x01010001 0x01010001>,
+				<0x0000002c 0x01010001 0x01010001>,
+				<0x00000030 0x01010001 0x01010001>,
+				<0x00000034 0x01010001 0x01010001>,
+				<0x00000038 0x01010001 0x01010001>,
+				<0x00000040 0x01010001 0x01010001>,
+				<0x00000044 0x01010001 0x01010001>,
+				<0x00000048 0x01010001 0x01010001>,
+				<0x0000004c 0x01010001 0x01010001>,
+				<0x00000054 0x01010001 0x01010001>,
+				<0x00000058 0x01010001 0x01010001>,
+				<0x0000005c 0x01010001 0x01010001>,
+				<0x00000060 0x01010001 0x01010101>,
+				<0x00000064 0x01010001 0x01010101>,
+				<0x00000068 0x01010001 0x01010101>,
+				<0x0000006c 0x01010001 0x01010101>,
+				<0x00000070 0x01010001 0x01010101>,
+				<0x00000074 0x01010001 0x01010101>,
+				<0x00000078 0x01010001 0x03010001>,
+				<0x00000090 0x01010001 0x01010001>,
+				<0x00000094 0x01010001 0x01010001>;
 			u-boot,dm-pre-reloc;
 		};
 
 		noc_fw_soc2fpga_soc2fpga_scr@ffd21200 {
 			reg = <0xffd21200 0x00000004>;
 			/* Disable soc2fpga security access */
-			intel,offset-settings = <0x00000000 0x0ffe0101>;
+			intel,offset-settings = <0x00000000 0x0ffe0101 0x0ffe0101>;
 			u-boot,dm-pre-reloc;
 		};
 
 		noc_fw_lwsoc2fpga_lwsoc2fpga_scr@ffd21300 {
 			reg = <0xffd21300 0x00000004>;
 			/* Disable lightweight soc2fpga security access */
-			intel,offset-settings = <0x00000000 0x0ffe0101>;
+			intel,offset-settings = <0x00000000 0x0ffe0101 0x0ffe0101>;
 			u-boot,dm-pre-reloc;
 		};
 
 		noc_fw_tcu_tcu_scr@ffd21400 {
 			reg = <0xffd21400 0x00000004>;
 			/* Disable DMA ECC security access, for SMMU use */
-			intel,offset-settings = <0x00000000 0x01010001>;
+			intel,offset-settings = <0x00000000 0x01010001 0x01010001>;
 			u-boot,dm-pre-reloc;
 		};
 
@@ -136,7 +138,7 @@ Path: arch/arm/dts/socfpga_soc64_u-boot.dtsi
 			reg = <0xffd24800 0x0000000c>;
 			intel,offset-settings =
 				/* Enable non-prviledged access to various periphs */
-				<0x00000000 0xfff73ffb>;
+				<0x00000000 0xfff73ffb 0xfff73ffb>;
 			u-boot,dm-pre-reloc;
 		};
 	};
@@ -149,10 +151,10 @@ Path: arch/arm/dts/socfpga_n5x-u-boot.dtsi
 			reg = <0xf7100200 0x00000014>;
 			intel,offset-settings =
 				/* Disable ocram security at CCU for non secure access */
-				<0x0000004 0x8000ffff>,
-				<0x0000008 0x8000ffff>,
-				<0x000000c 0x8000ffff>,
-				<0x0000010 0x8000ffff>;
+				<0x0000004 0x8000ffff 0xe007ffff>,
+				<0x0000008 0x8000ffff 0xe007ffff>,
+				<0x000000c 0x8000ffff 0xe007ffff>,
+				<0x0000010 0x8000ffff 0xe007ffff>;
 			u-boot,dm-pre-reloc;
 		};
 
@@ -160,9 +162,9 @@ Path: arch/arm/dts/socfpga_n5x-u-boot.dtsi
 			reg = <0xf8020000 0x0000001c>;
 			intel,offset-settings =
 				/* Disable MPFE firewall for SMMU */
-				<0x00000000 0x00010101>,
+				<0x00000000 0x00010101 0x00010101>,
 				/* Disable MPFE firewall for HMC adapter */
-				<0x00000004 0x00000001>;
+				<0x00000004 0x00000001 0x00010101>;
 			u-boot,dm-pre-reloc;
 		};
 	};
@@ -175,10 +177,10 @@ Path: arch/arm/dts/socfpga_agilex-u-boot.dtsi
 			reg = <0xf7100200 0x00000014>;
 			intel,offset-settings =
 				/* Disable ocram security at CCU for non secure access */
-				<0x0000004 0x8000ffff>,
-				<0x0000008 0x8000ffff>,
-				<0x000000c 0x8000ffff>,
-				<0x0000010 0x8000ffff>;
+				<0x0000004 0x8000ffff 0xe003ffff>,
+				<0x0000008 0x8000ffff 0xe003ffff>,
+				<0x000000c 0x8000ffff 0xe003ffff>,
+				<0x0000010 0x8000ffff 0xe003ffff>;
 			u-boot,dm-pre-reloc;
 		};
 
@@ -186,9 +188,9 @@ Path: arch/arm/dts/socfpga_agilex-u-boot.dtsi
 			reg = <0xf8020000 0x0000001c>;
 			intel,offset-settings =
 				/* Disable MPFE firewall for SMMU */
-				<0x00000000 0x00010101>,
+				<0x00000000 0x00010101 0x00010101>,
 				/* Disable MPFE firewall for HMC adapter */
-				<0x00000004 0x00000001>;
+				<0x00000004 0x00000001 0x00010101>;
 			u-boot,dm-pre-reloc;
 		};
 
@@ -202,25 +204,25 @@ Path: arch/arm/dts/socfpga_agilex-u-boot.dtsi
 		soc_noc_fw_ddr_fpga2sdram_inst_0_ddr_scr@f8020100 {
 			reg = <0xf8020100 0x00000050>;
 			intel,offset-settings =
-				<0x0000000 0x00000000>,
-				<0x0000004 0x00000000>,
-				<0x0000008 0x00000000>,
-				<0x0000010 0x00000000>,
-				<0x0000014 0x00000000>,
-				<0x0000018 0x0000ffff>,
-				<0x000001c 0x00000000>,
-				<0x0000020 0x00000000>,
-				<0x0000024 0x00000000>,
-				<0x0000028 0x0000ffff>,
-				<0x000002c 0x00000000>,
-				<0x0000030 0x00000000>,
-				<0x0000034 0x00000000>,
-				<0x0000038 0x0000ffff>,
-				<0x000003c 0x00000000>,
-				<0x0000040 0x00000000>,
-				<0x0000044 0x00000000>,
-				<0x0000048 0x0000ffff>,
-				<0x000004c 0x00000000>;
+				<0x0000000 0x00000000 0x0000000f>,
+				<0x0000004 0x00000000 0x0000000f>,
+				<0x0000008 0x00000000 0x0000000f>,
+				<0x0000010 0x00000000 0xffff0000>,
+				<0x0000014 0x00000000 0x000000ff>,
+				<0x0000018 0x00000000 0xffff0000>,
+				<0x000001c 0x00000000 0x000000ff>,
+				<0x0000020 0x00000000 0xffff0000>,
+				<0x0000024 0x00000000 0x000000ff>,
+				<0x0000028 0x00000000 0xffff0000>,
+				<0x000002c 0x00000000 0x000000ff>,
+				<0x0000030 0x00000000 0xffff0000>,
+				<0x0000034 0x00000000 0x000000ff>,
+				<0x0000038 0x00000000 0xffff0000>,
+				<0x000003c 0x00000000 0x000000ff>,
+				<0x0000040 0x00000000 0xffff0000>,
+				<0x0000044 0x00000000 0x000000ff>,
+				<0x0000048 0x00000000 0xffff0000>,
+				<0x000004c 0x00000000 0x000000ff>;
 			u-boot,dm-pre-reloc;
 		};
 
@@ -234,11 +236,11 @@ Path: arch/arm/dts/socfpga_agilex-u-boot.dtsi
 		soc_mpfe_noc_inst_0_ccu_mem0_I_main_QosGenerator@f8022080 {
 			reg = <0xf8022080 0x0000001c>;
 			intel,offset-settings =
-				<0x0000008 0x80000200>,
-				<0x000000c 0x00000003>,
-				<0x0000010 0x00000BFE>,
-				<0x0000014 0x00000008>,
-				<0x0000018 0x00000000>;
+				<0x0000008 0x00000200 0x00000303>,
+				<0x000000c 0x00000003 0x00000003>,
+				<0x0000010 0x00000BFE 0x00007fff>,
+				<0x0000014 0x00000008 0x000003ff>,
+				<0x0000018 0x00000000 0x0000000f>;
 			u-boot,dm-pre-reloc;
 		};
 	};
@@ -251,43 +253,43 @@ Path: arch/arm/dts/socfpga_stratix10-u-boot.dtsi
 			reg = <0xf7000000 0x00049e60>;
 			intel,offset-settings =
 				/* Enable access to DDR reg from CPU */
-				<0x0004400 0xF8000000>,
+				<0x0004400 0xF8000000 0xffffffff>,
 
 				/* Enable access to DDR region from CPU */
-				<0x00045c0 0x00000000>,
-				<0x00045e0 0x00000000>,
-				<0x0004600 0x00000000>,
-				<0x0004620 0x00000000>,
-				<0x0004640 0x00000000>,
-				<0x0004660 0x00000000>,
+				<0x00045c0 0x00000000 0xffffffdf>,
+				<0x00045e0 0x00000000 0xffffffdf>,
+				<0x0004600 0x00000000 0xffffffdf>,
+				<0x0004620 0x00000000 0xffffffdf>,
+				<0x0004640 0x00000000 0xffffffdf>,
+				<0x0004660 0x00000000 0xffffffdf>,
 
 				/* Disable ocram security at CCU for non secure access */
-				<0x0004688 0xfffc0000>,
-				<0x0018628 0xfffc0000>,
+				<0x0004688 0xfffc0000 0xffffffcf>,
+				<0x0018628 0xfffc0000 0xffffffcf>,
 
 				/* Enable access to DDR region from IO master */
-				<0x00018560 0x00000000>,
-				<0x00018580 0x00000000>,
-				<0x000185a0 0x00000000>,
-				<0x000185c0 0x00000000>,
-				<0x000185e0 0x00000000>,
-				<0x00018600 0x00000000>,
+				<0x00018560 0x00000000 0xffffffdf>,
+				<0x00018580 0x00000000 0xffffffdf>,
+				<0x000185a0 0x00000000 0xffffffdf>,
+				<0x000185c0 0x00000000 0xffffffdf>,
+				<0x000185e0 0x00000000 0xffffffdf>,
+				<0x00018600 0x00000000 0xffffffdf>,
 
 				/* Enable access to DDR region from TCU */
-				<0x0002c520 0x00000000>,
-				<0x0002c540 0x00000000>,
-				<0x0002c560 0x00000000>,
-				<0x0002c580 0x00000000>,
-				<0x0002c5a0 0x00000000>,
-				<0x0002c5c0 0x00000000>,
+				<0x0002c520 0x00000000 0xffffffdf>,
+				<0x0002c540 0x00000000 0xffffffdf>,
+				<0x0002c560 0x00000000 0xffffffdf>,
+				<0x0002c580 0x00000000 0xffffffdf>,
+				<0x0002c5a0 0x00000000 0xffffffdf>,
+				<0x0002c5c0 0x00000000 0xffffffdf>,
 
 				/* Enable access to DDR region from FPGA */
-				<0x000105a0 0x00000000>,
-				<0x000105c0 0x00000000>,
-				<0x000105e0 0x00000000>,
-				<0x00010600 0x00000000>,
-				<0x00010620 0x00000000>,
-				<0x00010640 0x00000000>;
+				<0x000105a0 0x00000000 0xffffffdf>,
+				<0x000105c0 0x00000000 0xffffffdf>,
+				<0x000105e0 0x00000000 0xffffffdf>,
+				<0x00010600 0x00000000 0xffffffdf>,
+				<0x00010620 0x00000000 0xffffffdf>,
+				<0x00010640 0x00000000 0xffffffdf>;
 			u-boot,dm-pre-reloc;
 		};
 
@@ -297,82 +299,81 @@ Path: arch/arm/dts/socfpga_stratix10-u-boot.dtsi
 		 *
 		 * Below are all fpga2sdram firewall settings with default
 		 * reset value for the sake of easy reference by users.
-		 * Users may choose to remove any of these register
-		 * configurations that they do not require in their specific
-		 * implementation.
+		 * Users may choose to remove any of these register configurations
+		 * that they do not require in their specific implementation.
 		 */
 		soc_noc_fw_ddr_fpga2sdram_inst_0_ddr_scr@f8020200 {
 			reg = <0xf8020200 0x00000050>;
 			intel,offset-settings =
-				<0x0000000 0x00000000>,
-				<0x0000004 0x00000000>,
-				<0x0000008 0x00000000>,
-				<0x0000010 0x00000000>,
-				<0x0000014 0x00000000>,
-				<0x0000018 0x0000ffff>,
-				<0x000001c 0x00000000>,
-				<0x0000020 0x00000000>,
-				<0x0000024 0x00000000>,
-				<0x0000028 0x0000ffff>,
-				<0x000002c 0x00000000>,
-				<0x0000030 0x00000000>,
-				<0x0000034 0x00000000>,
-				<0x0000038 0x0000ffff>,
-				<0x000003c 0x00000000>,
-				<0x0000040 0x00000000>,
-				<0x0000044 0x00000000>,
-				<0x0000048 0x0000ffff>,
-				<0x000004c 0x00000000>;
+				<0x0000000 0x00000000 0x0000000f>,
+				<0x0000004 0x00000000 0x0000000f>,
+				<0x0000008 0x00000000 0x0000000f>,
+				<0x0000010 0x00000000 0xffff0000>,
+				<0x0000014 0x00000000 0x0000001f>,
+				<0x0000018 0x00000000 0xffff0000>,
+				<0x000001c 0x00000000 0x0000001f>,
+				<0x0000020 0x00000000 0xffff0000>,
+				<0x0000024 0x00000000 0x0000001f>,
+				<0x0000028 0x00000000 0xffff0000>,
+				<0x000002c 0x00000000 0x0000001f>,
+				<0x0000030 0x00000000 0xffff0000>,
+				<0x0000034 0x00000000 0x0000001f>,
+				<0x0000038 0x00000000 0xffff0000>,
+				<0x000003c 0x00000000 0x0000001f>,
+				<0x0000040 0x00000000 0xffff0000>,
+				<0x0000044 0x00000000 0x0000001f>,
+				<0x0000048 0x00000000 0xffff0000>,
+				<0x000004c 0x00000000 0x0000001f>;
 			u-boot,dm-pre-reloc;
 		};
 
 		soc_noc_fw_ddr_fpga2sdram_inst_1_ddr_scr@f8020300 {
 			reg = <0xf8020300 0x00000050>;
 			intel,offset-settings =
-				<0x0000000 0x00000000>,
-				<0x0000004 0x00000000>,
-				<0x0000008 0x00000000>,
-				<0x0000010 0x00000000>,
-				<0x0000014 0x00000000>,
-				<0x0000018 0x0000ffff>,
-				<0x000001c 0x00000000>,
-				<0x0000020 0x00000000>,
-				<0x0000024 0x00000000>,
-				<0x0000028 0x0000ffff>,
-				<0x000002c 0x00000000>,
-				<0x0000030 0x00000000>,
-				<0x0000034 0x00000000>,
-				<0x0000038 0x0000ffff>,
-				<0x000003c 0x00000000>,
-				<0x0000040 0x00000000>,
-				<0x0000044 0x00000000>,
-				<0x0000048 0x0000ffff>,
-				<0x000004c 0x00000000>;
+				<0x0000000 0x00000000 0x0000000f>,
+				<0x0000004 0x00000000 0x0000000f>,
+				<0x0000008 0x00000000 0x0000000f>,
+				<0x0000010 0x00000000 0xffff0000>,
+				<0x0000014 0x00000000 0x0000001f>,
+				<0x0000018 0x00000000 0xffff0000>,
+				<0x000001c 0x00000000 0x0000001f>,
+				<0x0000020 0x00000000 0xffff0000>,
+				<0x0000024 0x00000000 0x0000001f>,
+				<0x0000028 0x00000000 0xffff0000>,
+				<0x000002c 0x00000000 0x0000001f>,
+				<0x0000030 0x00000000 0xffff0000>,
+				<0x0000034 0x00000000 0x0000001f>,
+				<0x0000038 0x00000000 0xffff0000>,
+				<0x000003c 0x00000000 0x0000001f>,
+				<0x0000040 0x00000000 0xffff0000>,
+				<0x0000044 0x00000000 0x0000001f>,
+				<0x0000048 0x00000000 0xffff0000>,
+				<0x000004c 0x00000000 0x0000001f>;
 			u-boot,dm-pre-reloc;
 		};
 
 		soc_noc_fw_ddr_fpga2sdram_inst_2_ddr_scr@f8020400 {
 			reg = <0xf8020400 0x00000050>;
 			intel,offset-settings =
-				<0x0000000 0x00000000>,
-				<0x0000004 0x00000000>,
-				<0x0000008 0x00000000>,
-				<0x0000010 0x00000000>,
-				<0x0000014 0x00000000>,
-				<0x0000018 0x0000ffff>,
-				<0x000001c 0x00000000>,
-				<0x0000020 0x00000000>,
-				<0x0000024 0x00000000>,
-				<0x0000028 0x0000ffff>,
-				<0x000002c 0x00000000>,
-				<0x0000030 0x00000000>,
-				<0x0000034 0x00000000>,
-				<0x0000038 0x0000ffff>,
-				<0x000003c 0x00000000>,
-				<0x0000040 0x00000000>,
-				<0x0000044 0x00000000>,
-				<0x0000048 0x0000ffff>,
-				<0x000004c 0x00000000>;
+				<0x0000000 0x00000000 0x0000000f>,
+				<0x0000004 0x00000000 0x0000000f>,
+				<0x0000008 0x00000000 0x0000000f>,
+				<0x0000010 0x00000000 0xffff0000>,
+				<0x0000014 0x00000000 0x0000001f>,
+				<0x0000018 0x00000000 0xffff0000>,
+				<0x000001c 0x00000000 0x0000001f>,
+				<0x0000020 0x00000000 0xffff0000>,
+				<0x0000024 0x00000000 0x0000001f>,
+				<0x0000028 0x00000000 0xffff0000>,
+				<0x000002c 0x00000000 0x0000001f>,
+				<0x0000030 0x00000000 0xffff0000>,
+				<0x0000034 0x00000000 0x0000001f>,
+				<0x0000038 0x00000000 0xffff0000>,
+				<0x000003c 0x00000000 0x0000001f>,
+				<0x0000040 0x00000000 0xffff0000>,
+				<0x0000044 0x00000000 0x0000001f>,
+				<0x0000048 0x00000000 0xffff0000>,
+				<0x000004c 0x00000000 0x0000001f>;
 			u-boot,dm-pre-reloc;
 		};
 
@@ -386,11 +387,11 @@ Path: arch/arm/dts/socfpga_stratix10-u-boot.dtsi
 		soc_ddr_scheduler_inst_0_ccu_mem0_I_main_QosGenerator@f8022080 {
 			reg = <0xf8022080 0x0000001c>;
 			intel,offset-settings =
-				<0x0000008 0x80000000>,
-				<0x000000c 0x00000001>,
-				<0x0000010 0x00000BFE>,
-				<0x0000014 0x00000008>,
-				<0x0000018 0x00000000>;
+				<0x0000008 0x00000000 0x00000303>,
+				<0x000000c 0x00000001 0x00000003>,
+				<0x0000010 0x00000BFE 0x00001fff>,
+				<0x0000014 0x00000008 0x000003ff>,
+				<0x0000018 0x00000000 0x00000007>;
 			u-boot,dm-pre-reloc;
 		};
 	};
diff --git a/drivers/misc/socfpga_secreg.c b/drivers/misc/socfpga_secreg.c
index 0ea30c254b..48ff80fd26 100644
--- a/drivers/misc/socfpga_secreg.c
+++ b/drivers/misc/socfpga_secreg.c
@@ -1,7 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2021 Intel Corporation <www.intel.com>
- *
+ * Copyright (C) 2021-2023 Intel Corporation <www.intel.com>
  */
 
 #include <asm/io.h>
@@ -10,11 +9,13 @@
 #include <errno.h>
 #include <linux/sizes.h>
 
+#define NUMBER_OF_ELEMENTS 3
+
 static int socfpga_secreg_probe(struct udevice *dev)
 {
 	const fdt32_t *list;
 	fdt_addr_t offset, base;
-	fdt_val_t val, read_val;
+	fdt_val_t val, read_val, mask, set_mask;
 	int size, i;
 	u32 blk_sz, reg;
 	ofnode node;
@@ -47,12 +48,26 @@ static int socfpga_secreg_probe(struct udevice *dev)
 
 		debug("%s(intel,offset-settings property size=%x)\n", __func__,
 		      size);
-		size /= sizeof(*list) * 2;
+		size /= sizeof(*list) * NUMBER_OF_ELEMENTS;
+
+		/*
+		 * First element: offset
+		 * Second element: val
+		 * Third element: mask
+		 */
 		for (i = 0; i < size; i++) {
 			offset = fdt32_to_cpu(*list++);
 			val = fdt32_to_cpu(*list++);
-			debug("%s(intel,offset-settings 0x%llx : 0x%llx)\n",
-			      __func__, offset, val);
+
+			/* Reads the masking bit value from the list */
+			mask = fdt32_to_cpu(*list++);
+
+			/*
+			 * Reads out the offsets, value and masking bits
+			 * Ex: <0x00000000 0x00000230 0xffffffff>
+			 */
+			debug("%s(intel,offset-settings 0x%llx : 0x%llx : 0x%llx)\n",
+			      __func__, offset, val, mask);
 
 			if (blk_sz < offset + SZ_4) {
 				printf("%s: Overflow as offset 0x%llx or reg",
@@ -62,12 +77,27 @@ static int socfpga_secreg_probe(struct udevice *dev)
 				return -EINVAL;
 			}
 
-			reg = base + offset;
-			writel(val, (uintptr_t)reg);
+			if (mask != 0) {
+				if (mask == 0xffffffff) {
+					reg = base + offset;
+					writel(val, (uintptr_t)reg);
+				} else {
+					/* Mask the value with the masking bits */
+					set_mask = val & mask;
+
+					reg = base + offset;
+
+					/* Clears and sets specific bits in the register */
+					clrsetbits_le32(reg, mask, set_mask);
+				}
+			}
 
 			read_val = readl((uintptr_t)reg);
+
+			/* Reads out the register, masked value and the read value */
 			debug("%s(reg 0x%x = wr : 0x%llx  rd : 0x%llx)\n",
-			      __func__, reg, val, read_val);
+			      __func__, reg, set_mask, read_val);
+
 		}
 	}