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* aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford2023-03-3010-448/+2088
* aarch64: Add the SME2 MOVA instructionsRichard Sandiford2023-03-3010-312/+674
* aarch64: Add support for predicate-as-counter registersRichard Sandiford2023-03-306-1597/+1647
* aarch64; Add support for vector offset rangesRichard Sandiford2023-03-301-9/+48
* aarch64: Add support for vgx2 and vgx4Richard Sandiford2023-03-301-8/+41
* aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_arrayRichard Sandiford2023-03-303-7/+7
* aarch64: Add a _10 suffix to FLD_imm3Richard Sandiford2023-03-306-8/+8
* aarch64: Prefer register ranges & support wrappingRichard Sandiford2023-03-301-1/+1
* aarch64: Add support for strided register listsRichard Sandiford2023-03-302-23/+56
* aarch64: Sort fields alphanumericallyRichard Sandiford2023-03-302-163/+164
* aarch64: Resync field namesRichard Sandiford2023-03-301-7/+7
* aarch64: Regularise FLD_* suffixesRichard Sandiford2023-03-306-55/+55
* aarch64: Add a aarch64_cpu_supports_inst_p helperRichard Sandiford2023-03-301-0/+13
* aarch64: Reorder some OP_SVE_* macrosRichard Sandiford2023-03-301-16/+16
* aarch64: Rename aarch64-tbl.h OP_SME_* macrosRichard Sandiford2023-03-301-81/+77
* aarch64: Try to report invalid variants against the closest matchRichard Sandiford2023-03-303-19/+30
* aarch64: Make AARCH64_OPDE_REG_LIST take a bitfieldRichard Sandiford2023-03-301-1/+1
* aarch64: Add an operand class for SVE register listsRichard Sandiford2023-03-303-14/+13
* aarch64: Commonise checks for index operandsRichard Sandiford2023-03-301-18/+32
* aarch64: Add an error code for out-of-range registersRichard Sandiford2023-03-301-6/+14
* aarch64: Move w12-w15 range check to libopcodesRichard Sandiford2023-03-301-6/+20
* aarch64: Move ZA range checks to aarch64-opc.cRichard Sandiford2023-03-303-25/+67
* aarch64: Make indexed_za use 64-bit immediatesRichard Sandiford2023-03-301-3/+3
* aarch64: Rename za_tile_vector to za_indexRichard Sandiford2023-03-303-36/+36
* aarch64: Treat ZA as a registerRichard Sandiford2023-03-302-2/+2
* aarch64: Make SME instructions use F_STRICTRichard Sandiford2023-03-303-57/+62
* aarch64: Restrict range of PRFM opcodesRichard Sandiford2023-03-301-0/+9
* aarch64: Fix PSEL opcode maskRichard Sandiford2023-03-301-1/+1
* aarch64: Add sme-i16i64 and sme-f64f64 aliasesRichard Sandiford2023-03-301-22/+22
* RISC-V: Fix disassemble fetch fail return value.Jiawei2023-03-211-2/+2
* x86: drop "shimm" special case template expansionsJan Beulich2023-03-201-15/+15
* x86: VexVVVV is now merely a booleanJan Beulich2023-03-203-260/+247
* x86: re-work build_modrm_byte()'s register assignmentJan Beulich2023-03-202-57/+57
* Revert "segfault at i386-dis.c:9815"Alan Modra2023-03-201-9/+4
* segfault at i386-dis.c:9815Alan Modra2023-03-191-4/+9
* cpu/mem.opc whitespace tidyAlan Modra2023-03-162-24/+23
* Fix an illegal memory access when disassembling a corrupt MeP file.Nick Clifton2023-03-152-0/+19
* Fix an illegal memory access when disassebling a corrupt ARM file.Nick Clifton2023-03-152-5/+17
* [Aarch64] Add Binutils support for MECRichard Ball2023-02-282-0/+13
* Updated Serbian translations for gold, gprof and opcodes sub-directoriesNick Clifton2023-02-271-300/+301
* opcodes/m68k: enable libopcodes styling for GDBAndrew Burgess2023-02-251-0/+5
* x86: MONITOR/MWAIT are not SSE3 insnsJan Beulich2023-02-245-7148/+7161
* x86-64: don't permit LAHF/SAHF with "generic64"Jan Beulich2023-02-245-5127/+5166
* x86: have insns acting on segment selector values allow for consistent operandsJan Beulich2023-02-242-897/+964
* x86: restrict insn templates accepting negative 8-bit immediatesJan Beulich2023-02-242-154/+154
* x86-64: LAR and LSL don't need REX.WJan Beulich2023-02-222-8/+8
* x86: optimize BT{,C,R,S} $imm,%regJan Beulich2023-02-222-8/+8
* opcodes: style m68k disassembler outputAndreas Schwab2023-02-201-116/+238
* x86: {LD,ST}TILECFG use an extension opcodeJan Beulich2023-02-142-4/+4
* PR30120: fix x87 fucomp misassembledMichael Matz2023-02-132-2/+2
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