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| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:10 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:10 +0100 |
| commit | 4eede8c2442115513a3f0c4f3610fbd6fe919a58 (patch) | |
| tree | 0dd36c53aa52fe9a8d739b2c55992abd30013612 /opcodes | |
| parent | f5b57feac2389eba64bea45f0115474fbbb13d8e (diff) | |
| download | binutils-gdb-4eede8c2442115513a3f0c4f3610fbd6fe919a58.tar.gz | |
aarch64: Prefer register ranges & support wrapping
Until now, binutils has supported register ranges such
as { v0.4s - v3.4s } as an unofficial shorthand for
{ v0.4s, v1.4s, v2.4s, v3.4s }. The SME2 ISA embraces this form
and makes it the preferred disassembly. It also embraces wrapped
lists such as { z31.s - z2.s }, which is something that binutils
didn't previously allow.
The range form was already binutils's preferred disassembly for 3- and
4-register lists. This patch prefers it for 2-register lists too.
The patch also adds support for wrap-around.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/aarch64-opc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 4e950cf70f8..1a1e1bd22f3 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -3246,7 +3246,7 @@ print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd, /* The hyphenated form is preferred for disassembly if there are more than two registers in the list, and the register numbers are monotonically increasing in increments of one. */ - if (stride == 1 && num_regs > 2 && last_reg > first_reg) + if (stride == 1 && num_regs > 1) snprintf (buf, size, "{%s-%s}%s", style_reg (styler, "%s%d.%s", prefix, first_reg, qlf_name), style_reg (styler, "%s%d.%s", prefix, last_reg, qlf_name), tb); |