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| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:08 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:08 +0100 |
| commit | 38c5aa5e88406193fe184a129cd397bc09c304e2 (patch) | |
| tree | e3efcdc0339a3d92042dc49a914acce4a46a6eef /opcodes | |
| parent | db3c06bf93f577b9eb40e2cc5d67bfd0671d3c11 (diff) | |
| download | binutils-gdb-38c5aa5e88406193fe184a129cd397bc09c304e2.tar.gz | |
aarch64: Make AARCH64_OPDE_REG_LIST take a bitfield
AARCH64_OPDE_REG_LIST took a single operand that specified the
expected number of registers. However, there are quite a few
SME2 instructions that have both 2-register forms and (separate)
4-register forms. If the user tries to use a 3-register list,
it isn't obvious which opcode entry they meant. Saying that we
expect 2 registers and saying that we expect 4 registers would
both be wrong.
This patch therefore switches the operand to a bitfield. If a
AARCH64_OPDE_REG_LIST is reported against multiple opcode entries,
the patch ORs up the expected lengths.
This has no user-visible effect yet. A later patch adds more error
strings, alongside tests that use them.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/aarch64-opc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index dfffbf6f6e5..590d227fde3 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -1438,7 +1438,7 @@ set_reg_list_error (aarch64_operand_error *mismatch_detail, int idx, if (mismatch_detail == NULL) return; set_error (mismatch_detail, AARCH64_OPDE_REG_LIST, idx, NULL); - mismatch_detail->data[0].i = expected_num; + mismatch_detail->data[0].i = 1 << expected_num; } static inline void |