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path: root/src/compiler/nir/nir_opcodes.py
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* nir: Make ALU descriptions machine-readableAlyssa Rosenzweig2023-05-121-102/+131
* nir: Allow adding descriptions to ALU opcodesAlyssa Rosenzweig2023-05-121-47/+55
* nir: Model AGX-specific multiply-shift-addAlyssa Rosenzweig2023-05-111-0/+8
* nir: fix constant-folding of 64-bit fpowErik Faye-Lund2023-05-021-1/+1
* nir: pack_(s|u)norm_2x16 support float16 as inputQiang Yu2023-03-281-5/+5
* nir: ifind_msb_rev can only have int32 sourcesIan Romanick2023-03-101-1/+1
* nir: Add extr_agx opcodeHampus Linander2023-02-041-0/+20
* nir: Eliminate nir_op_f2bIan Romanick2023-02-031-1/+1
* nir: Add pack_half_2x16_rtz_split opcode.Timur Kristóf2023-01-261-0/+3
* nir: Add Midgard-specific fsin/fcos opsAlyssa Rosenzweig2023-01-161-0/+5
* nir: Eliminate nir_op_i2bIan Romanick2022-12-141-1/+1
* nir: Fix ifind_msb_rev constant folding.Georg Lehmann2022-10-221-10/+6
* nir: allow 16-bit fsin_amd/fcos_amdRhys Perry2022-07-071-2/+2
* nir: rename fsin_r600/fcos_r600 to fsin_amd/fcos_amdRhys Perry2022-07-071-3/+3
* nir: fix documentation for uadd_carry and usub_borry opcodesIago Toral Quiroga2022-07-071-4/+4
* nir: Add and use algebraic property "is selection"Ian Romanick2022-06-221-9/+10
* nir: i32csel opcodes should compare with integer zeroIan Romanick2022-06-221-2/+2
* nir: Fix constant folding for non-32-bit ifind_msb and clzJason Ekstrand2022-05-101-2/+2
* nir/opcodes: fisfinite32 should return bool32Jason Ekstrand2022-04-161-1/+1
* nir: introduce nir_pack_{sint,uint}_2x16 instructionsSamuel Pitoiset2022-03-041-0/+12
* nir: Allow the _replicates opcodes to have num_components != 4.Emma Anholt2022-02-251-4/+2
* nir: All set-on-comparison opcodes can take all float typesIan Romanick2022-02-101-3/+3
* nir: add nir_op_fmulz and nir_op_ffmazRhys Perry2022-01-201-0/+27
* nir: fix constant expression of ibitfield_extractSamuel Pitoiset2021-11-161-1/+1
* nir: Add Mali-specific derivative opcodesAlyssa Rosenzweig2021-10-061-0/+4
* nir: add sdot_2x16 and udot_2x16 opcodesRhys Perry2021-09-031-0/+50
* nir: Add comment to explain the sad_u8x4 opcode.Timur Kristóf2021-09-011-0/+5
* nir: fix ifind_msb_rev by using appropriate typeFilip Gawin2021-08-261-1/+1
* nir/opcodes: Add integer dot-product opcodesIan Romanick2021-08-241-0/+107
* nir: intel/compiler: Add and use nir_op_pack_32_4x8_splitIan Romanick2021-08-181-0/+4
* nir: Initialize evaluate_cube_face_index_amd dst.x.Vinson Lee2021-08-121-0/+1
* nir/opcodes: Use u_intN_(min|max)Ian Romanick2021-08-101-4/+4
* nir: fix signed overflow for iadd constant foldingRhys Perry2021-08-091-1/+1
* nir: add 32-bit bool of fisfiniteDave Airlie2021-08-061-0/+1
* util: Add and use functions to calculate min and max int for a sizeIan Romanick2021-08-031-1/+1
* nir: Add new opcode for ternary additionSagar Ghuge2021-07-161-0/+3
* nir/ifind_msb_rev: fix input checkThomas H.P. Andersen2021-07-041-1/+1
* nir: Fix constant folding for irhadd/urhaddAlyssa Rosenzweig2021-07-021-2/+2
* nir: Require vectorized ALU ops to be all-or-nothingJason Ekstrand2021-06-211-0/+2
* nir,vc4: Suffix a bunch of unorm 4x8 opcodes _vc4Jason Ekstrand2021-06-211-45/+47
* nir,panfrost: Suffix fsat_signed and fclamp_pos with _maliJason Ekstrand2021-06-211-2/+4
* nir,amd: Suffix nir_op_cube_face_coord/index with _amdJason Ekstrand2021-06-211-2/+2
* nir: Add nir_op_sad_u8x4 which corresponds to AMD's v_sad_u8.Timur Kristóf2021-06-091-0/+18
* nir, nir/algebraic: add byte/word insertion instructionsRhys Perry2021-06-081-0/+4
* nir: Add relaxed 24bit opcodesJesse Natalie2021-05-051-0/+5
* nir/opcodes: Reword confusing commentAlyssa Rosenzweig2021-05-031-1/+1
* nir: Add fsin_agx opcodeAlyssa Rosenzweig2021-05-021-0/+7
* nir: Add a new opcode for [un]packing doublesJesse Natalie2021-04-091-0/+12
* nir: Add r600 specific sin and cos variantsGert Wollny2021-03-221-0/+6
* nir: Add opcodes for fused comp + csel and optimizationsGert Wollny2021-03-221-0/+6
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