| Commit message (Collapse) | Author | Age | Files | Lines |
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1.13
Increase the charging speed to 1C when temperatures allow
Reduce the amount of variables polled via the SMBus
Fixed an issue when batteries would not exit shipping mode
1.12
Revert the charging rate to 0.5C
Store the state of charging at 0xa0
1.11
Adjust the threshold for Hybrid Power to 1536MA
Adjust the threshold for Hybrid Power to be disable to 5 percent RSOC
1.10
Disable Hybrid Power when the RSOC is less than 20 percent
Only enable LEARN once when RSOC is greater than 50 percent
Dont query unused registers on the BQ24780S
1.07
Disable PD requests when a normal USB-C device is connected
Account for having two chargers connected
Optimise the charging calculations
1.06
Strip PD responses to only include valid bits
1.05
Fix the charging voltage to 13.2V
Only call Anx when USB-C PD chargers are connected
Disable Hybrid-Power when charging current is less that 1536
1.04
Store power related variables in the EC RAM and mirror them to EC memory
to avoid memory overflow to mitigate some strange behaviours when the EC
memory overflows
1.03
Improved the reliability of DC Jack charging by modifying it to 800MHz, 3A
Avoided charging stalling by continuously polling the SMBus after overcharge
protection is active
Exposed the behavior of overcharge protection to APCI
Set the charge LED to purple when overcharge protection is active
Modified fan curve
Ensured the trackpad is in the desired state by polling its state every 10ms
Set the brightness of the keyboard backlight to the maximum
Streamlined the system by removing unused SMM events
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3b08cb8b2b4e9e9836cd7e8c545fc83b2e0e3f99
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This version adds scramble switch to support both production build and
serial build, and also fixes fast-k single rank wrong register bit.
BUG=b:269049451,b:267590318
TEST=Single rank DRAM suspend/resume pass, enable/disable scramble pass
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I7bf751e19d6df32bbd40b9dacad16fb99253d2ae
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In addition to DRAM, DPM also needs to handle scramble enable or
disable.
BUG=b:269049451
TEST=build pass and confirm enable/disable scramble successfully
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I291376edacfd4ae959764dbeb9b5b03739e3f4d5
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Update CPU DVFS OPP table to enhance power saving. The current CPU OPP
voltage is conservative, so CPU OPP voltage can be further optimized for
power saving.
TEST=get "MediaTek MCUPM firmware: version 1.01.04" string by
`strings mcupm.bin | grep -i media`
TEST=boot to shell.
BUG=NONE
Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.corp-partner.google.com>
Change-Id: I2dbb67f3b72f4fe7de2418189ae79f2e3694d9fa
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Fix the PMIC MT6315 id bug when registering the MT6315 regulator.
BUG=b:249436110
TEST=Video playback works well on MT8186 and MT8186T Steelix after
executing suspend_stress_test.
TEST=get "MediaTek SSPM firmware: version 2.0.1" by
strings sspm.bin | grep version
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Change-Id: Ib5d3612ac488aa41a9bcd61ad1e59048d395a3ef
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ChromeOS requires a RO SPL table. Add it here so that it can be linked
in coreboot.
The SPL table contains a set of version numbers to prevent rollback
attacks. Updates with a value lower than the value in the table are
not allowed.
See the Versioned Chip Endorsement Key (VCEK) Certificate and KDS
Interface Specification. Document # 57230 Rev. 0.50 October 2021
https://web.archive.org/web/20221213033802/https://www.amd.com/system/files/TechDocs/57230.pdf
BUG=b:243470283
TEST=Build Skyrim BIOS image and boot to OS.
Change-Id: Iee897dd2c0943c17e81e02a4d6c6296b585e12af
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
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Add PMIC MT6315 support for SSPM.
BUG=b:249436110
TEST=test of suspend and resume pass.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Change-Id: I5cf5c0a46ce0af056dca6af7442a9ddb5be4b490
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The last_emi is unsupported in ChromeOS project, so EMI driver would
get a NULL address because no memory is reserved for last_emi. Add
error checking for last_emi to avoid null pointer issue.
BUG=b:233720142
TEST=Test of suspend resume passes.
Change-Id: I7ceb048fc8e393607cab5096e6be626b9e0de135
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
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1.02
Modified the F10 scan code for better compatibility
Modified the F12 scan code for better compatibility
Initialised the Keyboard Backlight from the EC to avoid problems when switching branch
1.01
Fix the backlight helper to remember the last state
Modified the scan code of the sysreq key
1.00
Initial release EC firmware for the StarBook Mk VI
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I557fd5cd3b987fb4d9a1fb0eaa0e442d94c848fe
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[ADL] 1.01:
Enable hybrid power - when the battery has more than 15% power, support
chargers that don't output the required 40W.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If2c6311af7744b6bd708c2084ce18fcfe13b8f5d
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The efuse memory address is wrong for MCUPM to access. Add the
offset to revise the efuse memory address.
TEST=boot to shell.
BUG=b:244250440
Change-Id: I6e1b873cffa2949997ff36346266446c9380ae04
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
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coreboot was spelled with a capital C in these files. We don't run the
linters on these files, but since they're part of a coreboot-owned repo,
let's fix them.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Icb1d6ee12057d552938496d198a17b6c8bfd93e8
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Add changelogs for the EC updates and update the versions to:
[ADL] 1.00:
Initial release firmware
[TGL] 1.03:
Initial release firmware for the StarBook Mk VI
[CML] 1.07:
Add support to set the maximum charge level of the battery
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2130852554388baf61b44091bfa827cb2b2f09e3
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ChromeOS requires a custom SPL table. Make that table available in
coreboot to link against.
Bug=b:245727030
Test=Boots
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I70dcb19983c970283ee887b78a18c0668e83d4b0
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For ChromeOS project, we need to use MCUPM firmware without mtk header.
TEST=boot to shell.
BUG=b:244250440
Change-Id: I9730a9e16642644dd5282bb6714e29cf6f6ce335
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
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Revise the latency offset in SYSRAM for CPUFreq to be consistent with
MT8195.
TEST=boot to shell.
BUG=b:244250440
Change-Id: Id2fee742b545d2b50595cf35baaf647008fd0e2e
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.corp-partner.google.com>
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This is a data file that gives configuration data to AMD's ABL,
the PSP AGESA Bootloader. As there is no code, there is no ABI,
license, or version number.
Specified contents describing memory initialization:
Memory is 2 channel, LPDDR5/LPDDR5x
The GPIOs to use for the SPD identifiers:
Bit 0: GPIO 144
Bit 1: GPIO 85
Bit 2: GPIO 79
Bit 3: GPIO 91
Contains 16 slots for possible SPD entries.
UMA size is set to 64MB.
eSPI I/O range address and size configuration.
MEMRESTORECTL is enabled to leverage MRC Cache.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia72eb4bd3ea74d813cad34e06fb0452814460144
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This blob includes both full calibration and fast calibration flow.
BUG=b:233720142
TEST=DRAM calibration pass
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I0a6c0085700cad4582de2d5b9c1a6a18e9313c35
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Add SPM firmware version: pcm_suspend_20220705_v2_MP.
SPM suspend can turn 26M clock off when system goes into suspend
to save power.
TEST=spm pc is 0x400 which is in idle state.
BUG=b:236331724
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I2221f757ebe29ba982b80291a3f2fbd314083615
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Add dpm.pm and dpm.dm to support DRAM power management.
TEST=build pass
BUG=b:233720142
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I5d6d27c7d06b91a6530f9e259ae7bb69f1f12c60
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Add sspm.bin to support suspend/resume.
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ib10b9a9446ce7c057182e5ae0c087c4685db7f3f
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Add mcupm.bin initial version.
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Idf21e2e79a02478621c09b02d068c6eed94beee5
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Add README.md and license.txt.
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia5b394f463ed8c508bbe384383d8f3f6f1e2a523
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Since switching to upstream edk2, the extra padding that was added
to overcome MrChromebox’s hardcoded options is no longer needed.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia2740b8082131d1dc9cca71cd5049f29914d3e62
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1.07 has the following changes:
* Add support to set the maximum charge level of the battery
* Add Q Event for Touchpad State which allows it to be saved on
reboot
* Updated power configuration
* Use battery as a power source when the charger doesn't supply
enough output
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9b7cba104f347b31e075e18f0d5b1bdc8cb406ad
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1.03 contains the following changes:
* Fixed issue where keyboard backlight wouldn't turn off when
entering S3 or turning off
* Update Normal and Quiet fan curves to delay start until 65
degrees. Performance mode is unchanged.
* Added support to select maximum charge percentage
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia478540ef0a850de27d1dd34e40fd7fe8ccfbbba
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The LabTop was renamed to the StarBook in its 5th generation, so this
change makes the folder more correct.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I97dbd66ec5b0acd68ca029dd156f8c8c5409ee88
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This reverts commit d13ba18eb0daaa6d6cd708bb981ee0a562ac4789.
Revert reason:
CB:62327 was created to fix a suspend failure issue, where we disable
26M clock to bypass pmic wrap when suspending. However, it turns out
that the root cause of the suspend issue is an incorrect pmif setting,
which is fixed in CB:63089. Therefore, revert CB:62327 to enable 26M
clock.
BUG=b:215639203
TEST=test of suspend and resume pass.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I63923188b814f0b44690784b55bcec9aff9b3d23
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The existing APCB file only has 4 SPD slots. This will not be enough
for DeWatt devices due to upcoming changes in how RAM IDs are allocated
for that variant. This commit updates the APCB file to have 16 slots
which is sufficient for DeWatt.
BUG=b:224884904
TEST=Used apcb_v3_edit to verify that the APCB file has 16 slots,
checked that AP firmware images built with this file boot correctly
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: Ifbfe2c61c42cd503a70fd84c51ce184c40fed318
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Refactor dramc_param to share more structures (CB:61293).
BUG=b:218577927
TEST=dram calibration pass
Cq-Depend: chromium:3504704
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I05aac544fa3749c6d43dec2df034e1ebe265ebeb
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The SRCLKENA0 is not pulled down when suspending. The root cause is that
26MHz clock is not disabled when suspending, so we update SPM firmware
to fix this issue.
TEST=verify 26MHz clock off using the oscilloscope.
BUG=b:215639203
Signed-off-by: Jason-ch Chen <jason-ch.chen@mediatek.com>
Change-Id: Iccaea858ff37cc3934c9a9a64bce7edf7cb0fbf1
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This SPL table is for all the Guybrush Chromebook.
BUG=b:216096562
Change-Id: I651bc76ca8f71ea842ca9ddb4ba99cfe03fc31bb
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
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Move some structures to common folder (CB:61132).
BUG=b:218577927
TEST=dram calibration pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: If0e48b914fa951b4fc07ff1f25c4b4837131508a
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This blob includes both full calibration and fast calibration flow.
TEST=DRAM calibration pass
BUG=b:204226005
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.com>
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I010ded1cb68f4bd50f08927b0b4faaa9b9db67f6
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TEST=build pass
BUG=none
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I6fdd88e40a623e6268c685630a7987ba45efc66c
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Add sspm.bin to support suspend/resume.
TEST=build pass
BUG=b:202871018
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.corp-partner.google.com>
Change-Id: Iae24878e1812c1e9e39ce8151c59e0ec2f234031
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SPM suspend can turn 26M clock off when system goes into suspend
to save power.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I5a35f1c10886d31da9ba6dfec5ee2b3cf0664563
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Add README.md and license.txt.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic6198353b1f7cca683875339a5fc4378a783d7a2
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Changes:
- Support CPU frequency for both 3.0G and 2.6G.
BUG=b:201598555
TEST=boot to shell
Change-Id: Ib4f93fda04836b6e41589ec82f80cd48cbcde13c
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See the README file for details.
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I58f893fcee785c1f44cf176b4954964aa77a217a
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Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.com>
Change-Id: I73e0b865bc018b6b67ab2ce67596e3fe98c48979
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Update mcupm.bin version to v1.01.00.
BUG=b:193000572
TEST=boot to shell
Change-Id: Ib8da62875bedf5090ef458876c4bdd2503d6dc97
Signed-off-by: Ben Tseng <ben.tseng@mediatek.corp-partner.google.com>
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Add logo for Tianocore splash
Add EC binary for TGL and CML
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I83cab8e0c84ffe512d5538de88ef42da6a29e3a4
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SPM suspend can turn 26M clock off when system goes into suspend
to save power.
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: If3ae0eb24f4990397e72d2acfa56a923cdd885e4
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Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Change-Id: I2b21d1edc2498e8c75ef4ceb3c9683847a171f4a
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Add mcupm.bin version v1.00.00.
Signed-off-by: Alex Miao <alex.miao@mediatek.corp-partner.google.com>
Change-Id: Id87cd5ce49b48de7ea45acc71462caa6d7dec61c
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Add README.md and license.txt.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I7d3c036938b169191b8d14c2ce894230e099d5ce
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Changes from 1.00.06 to 1.00.07:
- Add 2.6G CPU DVFS segment.
Signed-off-by: Andrew SH Cheng <andrew-sh.cheng@mediatek.com>
Change-Id: I4ecd0e816e7b12918470ac39afbded2105f8a4e7
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This fixes the auto reboot issue for Spherion.
BUG=b:186363855
TEST=Hayato boots
Change-Id: I143cb55cd63f5cc3b1820317c96aa3ef4af70f55
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
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This fixes memory training for DRAM Micron 8GB.
BUG=b:186363844
TEST=Hayato boots
Change-Id: I29f849bea76b4f5b0f1d8eac0b8c53c5cc3633ec
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
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