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| author | Martin Roth <gaumless@gmail.com> | 2022-09-03 17:55:08 -0600 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-09-09 17:37:02 +0000 |
| commit | 835f951f295e34d3579f1f9f2e1f11f0c3b085cd (patch) | |
| tree | 54bb92d602f4eaa6be2d82b73c0ede3d65c5e053 | |
| parent | 4635ce0d62f056c002b1082c51e2b606c096b913 (diff) | |
| download | blobs-835f951f295e34d3579f1f9f2e1f11f0c3b085cd.tar.gz | |
mb/google/skyrim: Add initial APCB release for skyrim board
This is a data file that gives configuration data to AMD's ABL,
the PSP AGESA Bootloader. As there is no code, there is no ABI,
license, or version number.
Specified contents describing memory initialization:
Memory is 2 channel, LPDDR5/LPDDR5x
The GPIOs to use for the SPD identifiers:
Bit 0: GPIO 144
Bit 1: GPIO 85
Bit 2: GPIO 79
Bit 3: GPIO 91
Contains 16 slots for possible SPD entries.
UMA size is set to 64MB.
eSPI I/O range address and size configuration.
MEMRESTORECTL is enabled to leverage MRC Cache.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia72eb4bd3ea74d813cad34e06fb0452814460144
| -rw-r--r-- | mainboard/google/skyrim/APCB_MDN_D5.bin | bin | 0 -> 39204 bytes | |||
| -rw-r--r-- | mainboard/google/skyrim/Release.txt | 25 |
2 files changed, 25 insertions, 0 deletions
diff --git a/mainboard/google/skyrim/APCB_MDN_D5.bin b/mainboard/google/skyrim/APCB_MDN_D5.bin Binary files differnew file mode 100644 index 0000000..2e58266 --- /dev/null +++ b/mainboard/google/skyrim/APCB_MDN_D5.bin diff --git a/mainboard/google/skyrim/Release.txt b/mainboard/google/skyrim/Release.txt new file mode 100644 index 0000000..fb5149d --- /dev/null +++ b/mainboard/google/skyrim/Release.txt @@ -0,0 +1,25 @@ +Files: + APCB_MDN_D5.bin - Data only - No license, ABI or Version # + +2022-09-02: Initial public release: +- Add APCB_MDN_D5.bin + This is a data file that gives configuration data to AMD's ABL, + the PSP AGESA Bootloader. As there is no code, there is no ABI, + license, or version number. + + Specified contents describing memory initialization: + Memory is 2 channel, LPDDR5/LPDDR5x + + The GPIOs to use for the SPD identifiers: + Bit 0: GPIO 144 + Bit 1: GPIO 85 + Bit 2: GPIO 79 + Bit 3: GPIO 91 + + Contains 16 slots for possible SPD entries. + UMA size is set to 64MB. + eSPI I/O range address and size configuration. + MEMRESTORECTL is enabled to leverage MRC Cache. + +sha1sum: +a91237472d662b8035450e19f118adaece4748f4 APCB_MDN_D5.bin |