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path: root/opcodes/mips-dis.c
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* opcodes/mips: disassemble unknown micromips instructions as two shortsAndrew Burgess2023-02-131-5/+8
* Update year range in copyright notice of binutils filesAlan Modra2023-01-011-1/+1
* libopcodes/mips: add support for disassembler stylingAndrew Burgess2022-12-051-109/+196
* opcodes/mips: use .word/.short for undefined instructionsAndrew Burgess2022-12-051-3/+6
* opcodes: Add non-enum disassembler optionsTsukasa OI2022-09-061-0/+2
* Update year range in copyright notice of binutils filesAlan Modra2022-01-021-1/+1
* Correct gs264e bfd_mach in mips_arch_choices.Chenghua Xu2021-07-271-1/+1
* MIPS/opcodes: Add legacy CP1 control register namesMaciej W. Rozycki2021-05-291-25/+37
* MIPS/opcodes: Do not use CP0 register names for control registersMaciej W. Rozycki2021-05-291-1/+6
* MIPS/opcodes: Add TX39 CP0 register namesMaciej W. Rozycki2021-05-291-1/+13
* Use bool in opcodesAlan Modra2021-03-311-38/+38
* Add startswith function and use it instead of CONST_STRNEQ.Martin Liska2021-03-221-9/+9
* Update year range in copyright notice of binutils filesAlan Modra2021-01-011-1/+1
* Update year range in copyright notice of binutils filesAlan Modra2020-01-011-1/+1
* mips bfd.h tidyAlan Modra2019-09-231-2/+3
* Add load-link, store-conditional paired EVA instructionsFaraz Shahbazker2019-05-061-3/+7
* [MIPS] fix typo in mips_arch_choices.Chenghua Xu2019-01-201-3/+3
* Update year range in copyright notice of binutils filesAlan Modra2019-01-011-1/+1
* [MIPS] Add Loongson 2K1000 proccessor support.Chenghua Xu2018-08-291-0/+5
* [MIPS] Add Loongson 3A2000/3A3000 proccessor support.Chenghua Xu2018-08-291-0/+5
* [MIPS] Add Loongson 3A1000 proccessor support.Chenghua Xu2018-08-291-1/+7
* [MIPS/GAS] Add Loongson EXT2 Instructions support.Chenghua Xu2018-08-291-0/+11
* [MIPS/GAS] Split Loongson EXT Instructions from loongson3a.Chenghua Xu2018-08-291-1/+11
* [MIPS/GAS] Split Loongson CAM Instructions from loongson3aChenghua Xu2018-08-291-2/+13
* MIPS/GAS: Split Loongson MMI Instructions from loongson2f/3aChenghua Xu2018-07-201-2/+12
* GDB PR tdep/8282: MIPS: Wire in `set disassembler-options'Maciej W. Rozycki2018-07-021-52/+158
* MIPS/opcodes: Fix a typo in `-M ginv' option descriptionMaciej W. Rozycki2018-06-211-1/+1
* MIPS: Add Global INValidate ASE supportFaraz Shahbazker2018-06-141-2/+12
* MIPS: Add CRC ASE supportScott Egerton2018-06-131-2/+3
* Update year range in copyright notice of binutils filesAlan Modra2018-01-031-1/+1
* MIPS: Fix XPA base and Virtualization ASE instruction handlingMaciej W. Rozycki2017-06-301-16/+32
* MIPS/opcodes: Correctly combine ASE flags for ASE_MIPS16E2_MT calculationMaciej W. Rozycki2017-06-301-3/+13
* MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor supportMaciej W. Rozycki2017-06-281-71/+109
* Don't use print_insn_XXX in GDBYao Qi2017-06-141-1/+1
* MIPS16e2: Add MIPS16e2 ASE supportMaciej W. Rozycki2017-05-151-16/+72
* MIPS/opcodes: Remove an incorrect MT ASE reference in MFC0/MTC0 decodingMaciej W. Rozycki2017-05-151-1/+1
* MIPS16/opcodes: Keep the LSB of PC-relative offsets in disassemblyMaciej W. Rozycki2017-05-021-3/+4
* MIPS16/opcodes: Add `-M no-aliases' disassembler option help textMaciej W. Rozycki2017-04-251-0/+3
* Update year range in copyright notice of all files.Alan Modra2017-01-021-1/+1
* MIPS16: Simplify extended operand handlingMaciej W. Rozycki2016-12-231-19/+17
* MIPS16: Handle non-extensible instructions correctlyMaciej W. Rozycki2016-12-231-0/+1
* opcodes: Use autoconf to check for `bfd_mips_elf_get_abiflags' in BFDMaciej W. Rozycki2016-12-231-5/+6
* MIPS16/opcodes: Respect ISA and ASE in disassemblyMaciej W. Rozycki2016-12-201-1/+4
* MIPS16: Switch to 32-bit opcode table interpretationMaciej W. Rozycki2016-12-201-78/+74
* MIPS/opcodes: Only examine ELF file structures if SYMTAB_AVAILABLEMaciej W. Rozycki2016-12-191-1/+1
* MIPS/opcodes: Only call `bfd_mips_elf_get_abiflags' if BFD64Maciej W. Rozycki2016-12-191-2/+9
* MIPS/opcodes: Also set disassembler's ASE flags from ELF structuresMaciej W. Rozycki2016-12-141-2/+42
* MIPS/opcodes: Reorder ELF file header flag handling in disassemblerMaciej W. Rozycki2016-12-141-13/+13
* MIPS16/opcodes: Reformat raw EXTEND and undecoded outputMaciej W. Rozycki2016-12-091-4/+4
* MIPS16/opcodes: Fix off-by-one indentation in `print_mips16_insn_arg'Maciej W. Rozycki2016-12-081-30/+30
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