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| author | Maciej W. Rozycki <macro@orcam.me.uk> | 2021-05-29 03:26:32 +0200 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@orcam.me.uk> | 2021-05-29 03:26:32 +0200 |
| commit | a3fb396f2dc57f585a49091e12ec6c588c45e681 (patch) | |
| tree | 3672573d24c85cb9157ad2c5f4a8b9ceb4945fe3 /opcodes/mips-dis.c | |
| parent | 9623cc5d1fb947daf6a0eadb4f7662d0791f7893 (diff) | |
| download | binutils-gdb-a3fb396f2dc57f585a49091e12ec6c588c45e681.tar.gz | |
MIPS/opcodes: Add TX39 CP0 register names
The TX39 core has its distinct set of CP0 registers[1], so it needs a
separate table to hold their names. Add a test case accordingly.
References:
[1] "32-Bit RISC Microprocessor TX39 Family Core Architecture User's
Manual", Toshiba, Jul. 27, 1995, Section 2.2.2 "System control
coprocessor (CP0) registers", pp. 9-10
opcodes/
* mips-dis.c (mips_cp0_names_r3900): New variable.
(mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
for "r3900".
gas/
* testsuite/gas/mips/cp0-names-r3900.d: New test.
* testsuite/gas/mips/mips.exp: Run it.
Diffstat (limited to 'opcodes/mips-dis.c')
| -rw-r--r-- | opcodes/mips-dis.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index d51942035b5..0bdf7cf8b8d 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -122,6 +122,18 @@ static const char * const mips_cp1_names_numeric[32] = "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" }; +static const char * const mips_cp0_names_r3900[32] = +{ + "$0", "$1", "$2", "c0_config", + "$4", "$5", "$6", "c0_cache", + "c0_badvaddr", "$9", "$10", "$11", + "c0_sr", "c0_cause", "c0_epc", "c0_prid", + "c0_debug", "c0_depc", "$18", "$19", + "$20", "$21", "$22", "$23", + "$24", "$25", "$26", "$27", + "$28", "$29", "$30", "$31", +}; + static const char * const mips_cp0_names_r3000[32] = { "c0_index", "c0_random", "c0_entrylo", "$3", @@ -457,7 +469,7 @@ const struct mips_arch_choice mips_arch_choices[] = mips_cp0_names_r3000, NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric }, { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 0, - mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_cp0_names_r3900, NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric }, { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 0, mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric, |