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| author | Maciej W. Rozycki <macro@imgtec.com> | 2017-06-30 00:55:07 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@imgtec.com> | 2017-06-30 00:55:07 +0100 |
| commit | 60804c53a0c365f0802e90c12dfcbe6696b861fe (patch) | |
| tree | de4dd080541708b2341d8a7df1f3a3a460aeb8f8 /opcodes/mips-dis.c | |
| parent | 92cebb3dbea282bbf7357ed2f3f03bc92fee8c7b (diff) | |
| download | binutils-gdb-60804c53a0c365f0802e90c12dfcbe6696b861fe.tar.gz | |
MIPS/opcodes: Correctly combine ASE flags for ASE_MIPS16E2_MT calculation
Correct a commit 25499ac7ee92 ("MIPS16e2: Add MIPS16e2 ASE support")
disassembler bug with the handling of the ASE_MIPS16E2_MT combination
ASE flag, where the calculation uses MIPS ABI Flags directly rather than
calculated internal ASE flags. Consequently code does not correctly set
the ASE_MIPS16E2_MT flag when the MIPS16e2 ASE flag and the MT ASE flag
come from different sources, i.e. one from the BFD chosen and the other
one from MIPS ABI Flags.
Fix this by using internal ASE_MT and ASE_MIPS16E2 flags in a separate
subsequent step, factored out to a dedicated function for use with
future combination ASE flags. Adjust the `mips16e2@mips16e2-mt-sub.d'
test case accordingly, where the MT flag comes from the BFD selected for
the disassembler and the MIPS16e2 flag comes from the ELF binary itself.
opcodes/
* mips-dis.c (mips_calculate_combination_ases): New function.
(mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
calculation to the new function.
(set_default_mips_dis_options): Call the new function.
gas/
* testsuite/gas/mips/mips16e2@mips16e2-mt-sub.d: Adjust for the
ASE_MIPS16E2_MT flag disassembler fix.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e2-mt-sub.d:
Likewise.
Diffstat (limited to 'opcodes/mips-dis.c')
| -rw-r--r-- | opcodes/mips-dis.c | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index e19d59a703d..588247a9bb4 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -805,12 +805,21 @@ mips_convert_abiflags_ases (unsigned long afl_ases) opcode_ases |= ASE_DSPR3; if (afl_ases & AFL_ASE_MIPS16E2) opcode_ases |= ASE_MIPS16E2; - if ((afl_ases & (AFL_ASE_MIPS16E2 | AFL_ASE_MT)) - == (AFL_ASE_MIPS16E2 | AFL_ASE_MT)) - opcode_ases |= ASE_MIPS16E2_MT; return opcode_ases; } +/* Calculate combination ASE flags from regular ASE flags. */ + +static unsigned long +mips_calculate_combination_ases (unsigned long opcode_ases) +{ + unsigned long combination_ases = 0; + + if ((opcode_ases & (ASE_MIPS16E2 | ASE_MT)) == (ASE_MIPS16E2 | ASE_MT)) + combination_ases |= ASE_MIPS16E2_MT; + return combination_ases; +} + static void set_default_mips_dis_options (struct disassemble_info *info) { @@ -880,6 +889,7 @@ set_default_mips_dis_options (struct disassemble_info *info) mips_ase |= ASE_MDMX; } #endif + mips_ase |= mips_calculate_combination_ases (mips_ase); } static void |