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path: root/opcodes/i386-gen.c
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* Support Intel AMX-COMPLEXHaochen Jiang2023-04-071-0/+3
* x86: introduce .insn directiveJan Beulich2023-03-311-0/+3
* x86: MONITOR/MWAIT are not SSE3 insnsJan Beulich2023-02-241-6/+7
* x86-64: don't permit LAHF/SAHF with "generic64"Jan Beulich2023-02-241-4/+5
* x86: drop use of VEX3SOURCESJan Beulich2023-02-101-1/+0
* x86: move (and rename) opcodespace attributeJan Beulich2023-02-101-19/+53
* x86: remove internationalization from i386-gen.cJan Beulich2023-01-271-26/+23
* x86: split i386-gen's opcode hash entry structJan Beulich2023-01-201-23/+28
* x86: absorb allocation in i386-genJan Beulich2023-01-201-2/+5
* x86: re-use insn mnemonic strings as much as possibleJan Beulich2023-01-201-4/+37
* x86: move insn mnemonics to a separate tableJan Beulich2023-01-201-4/+47
* Update year range in copyright notice of binutils filesAlan Modra2023-01-011-2/+2
* x86: correct/improve TSX controlsJan Beulich2022-12-221-0/+4
* x86: add dependencies on SVMEJan Beulich2022-12-221-0/+6
* x86: add dependencies on VMXJan Beulich2022-12-221-0/+4
* x86: correct XSAVE* dependenciesJan Beulich2022-12-221-1/+3
* x86: correct dependencies of a few AVX512 sub-featuresJan Beulich2022-12-221-4/+4
* x86: add dependencies on AVX2Jan Beulich2022-12-221-0/+4
* x86: correct SSE dependenciesJan Beulich2022-12-221-0/+8
* x86: re-work ISA extension dependency handlingJan Beulich2022-12-221-469/+328
* x86: rename CheckRegSize to CheckOperandSizeJan Beulich2022-12-211-1/+1
* x86: omit Cpu prefixes from opcode tableJan Beulich2022-12-191-346/+349
* x86: change representation of extension opcodeJan Beulich2022-12-161-3/+6
* x86: generate template sets data at build timeJan Beulich2022-12-121-1/+21
* x86: drop sentinel from i386_optab[]Jan Beulich2022-12-121-10/+0
* x86: instantiate i386_{op,reg}tab[] in gas instead of in libopcodesJan Beulich2022-12-121-3/+3
* x86: drop most OPERAND_TYPE_* (and rework the rest)Jan Beulich2022-12-021-103/+0
* x86: drop No_ldSufJan Beulich2022-12-011-1/+0
* x86: drop FloatRJan Beulich2022-11-301-1/+0
* Add AMD znver4 processor supportTejas Joshi2022-11-151-0/+5
* x86: fold special-operand insn attributes into a single enumJan Beulich2022-11-141-9/+1
* Support Intel RAO-INTKong Lingling2022-11-081-0/+5
* Support Intel AVX-NE-CONVERTkonglin12022-11-041-1/+6
* Support Intel MSRLISTHu, Lin12022-11-021-0/+5
* Support Intel WRMSRNSHu, Lin12022-11-021-0/+5
* Support Intel CMPccXADDHaochen Jiang2022-11-021-0/+5
* Support Intel AVX-VNNI-INT8Cui,Lili2022-11-021-1/+6
* Support Intel AVX-IFMAHongyu Wang2022-11-021-1/+6
* x86: minor improvements to optimize_imm() (part III)Jan Beulich2022-10-311-2/+0
* Support Intel PREFETCHICui, Lili2022-10-311-0/+3
* Support Intel AMX-FP16Cui,Lili2022-10-211-1/+4
* x86: re-work AVX-VNNI supportJan Beulich2022-10-201-1/+0
* x86: Disable AVX-VNNI when disabling AVX2H.J. Lu2022-10-181-1/+1
* x86: correct CPU_AMX_{BF16,INT8}_FLAGSJan Beulich2022-10-181-2/+2
* x86/Intel: restrict suffix derivationJan Beulich2022-09-301-2/+0
* x86: template-ize certain vector conversion insnsJan Beulich2022-08-161-4/+26
* x86: template-ize packed/scalar vector floating point insnsJan Beulich2022-08-161-19/+24
* revert "x86: Also pass -P to $(CPP) when processing i386-opc.tbl"Jan Beulich2022-08-161-8/+27
* x86: re-order insn template fieldsJan Beulich2022-07-181-2/+2
* x86: fold Disp32S and Disp32Jan Beulich2022-07-041-14/+8