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| author | Jan Beulich <jbeulich@suse.com> | 2022-07-04 08:32:50 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2022-07-04 08:32:50 +0200 |
| commit | a775efc84d0f15f7003fdab1592586b6fa8987cd (patch) | |
| tree | 248fd99caba89a053e9409d8d438cca6ea189f76 /opcodes/i386-gen.c | |
| parent | 02b83698ef04a33a8c606efeceb8fe7cd9a9b344 (diff) | |
| download | binutils-gdb-a775efc84d0f15f7003fdab1592586b6fa8987cd.tar.gz | |
x86: fold Disp32S and Disp32
The only case where 64-bit code uses non-sign-extended (can also be
considered zero-extended) displacements is when an address size override
is in place for a memory operand (i.e. particularly excluding
displacements of direct branches, which - if at all - are controlled by
operand size, and then are still sign-extended, just from 16 bits).
Hence the distinction in templates is unnecessary, allowing code to be
simplified in a number of places. The only place where logic becomes
more complicated is when signed-ness of relocations is determined in
output_disp().
The other caveat is that Disp64 cannot be specified anymore in an insn
template at the same time as Disp32. Unlike for non-64-bit mode,
templates don't specify displacements for both possible addressing
modes; the necessary adjustment to the expected ones has already been
done in match_template() anyway (but of course the logic there needs
tweaking now). Hence the single template so far doing so is split.
Diffstat (limited to 'opcodes/i386-gen.c')
| -rw-r--r-- | opcodes/i386-gen.c | 22 |
1 files changed, 8 insertions, 14 deletions
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 1fe59e6cc14..36cab20a1dd 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -475,8 +475,6 @@ static initializer operand_type_init[] = "Disp16" }, { "OPERAND_TYPE_DISP32", "Disp32" }, - { "OPERAND_TYPE_DISP32S", - "Disp32S" }, { "OPERAND_TYPE_DISP64", "Disp64" }, { "OPERAND_TYPE_INOUTPORTREG", @@ -520,7 +518,7 @@ static initializer operand_type_init[] = { "OPERAND_TYPE_DISP16_32", "Disp16|Disp32" }, { "OPERAND_TYPE_ANYDISP", - "Disp8|Disp16|Disp32|Disp32S|Disp64" }, + "Disp8|Disp16|Disp32|Disp64" }, { "OPERAND_TYPE_IMM16_32", "Imm16|Imm32" }, { "OPERAND_TYPE_IMM16_32S", @@ -529,14 +527,14 @@ static initializer operand_type_init[] = "Imm16|Imm32|Imm32S" }, { "OPERAND_TYPE_IMM32_64", "Imm32|Imm64" }, - { "OPERAND_TYPE_IMM32_32S_DISP32S", - "Imm32|Imm32S|Disp32S" }, + { "OPERAND_TYPE_IMM32_32S_DISP32", + "Imm32|Imm32S|Disp32" }, { "OPERAND_TYPE_IMM64_DISP64", "Imm64|Disp64" }, - { "OPERAND_TYPE_IMM32_32S_64_DISP32S", - "Imm32|Imm32S|Imm64|Disp32S" }, - { "OPERAND_TYPE_IMM32_32S_64_DISP32S_64", - "Imm32|Imm32S|Imm64|Disp32S|Disp64" }, + { "OPERAND_TYPE_IMM32_32S_64_DISP32", + "Imm32|Imm32S|Imm64|Disp32" }, + { "OPERAND_TYPE_IMM32_32S_64_DISP32_64", + "Imm32|Imm32S|Imm64|Disp32|Disp64" }, { "OPERAND_TYPE_ANYIMM", "Imm1|Imm8|Imm8S|Imm16|Imm32|Imm32S|Imm64" }, }; @@ -786,7 +784,6 @@ static bitfield operand_types[] = BITFIELD (Disp8), BITFIELD (Disp16), BITFIELD (Disp32), - BITFIELD (Disp32S), BITFIELD (Disp64), BITFIELD (Byte), BITFIELD (Word), @@ -1343,10 +1340,7 @@ process_i386_operand_type (FILE *table, char *op, enum stage stage, if (!active_cpu_flags.bitfield.cpu64 && !active_cpu_flags.bitfield.cpumpx) set_bitfield("Disp16", types, 1, ARRAY_SIZE (types), lineno); - if (!active_cpu_flags.bitfield.cpu64) - set_bitfield("Disp32", types, 1, ARRAY_SIZE (types), lineno); - if (!active_cpu_flags.bitfield.cpuno64) - set_bitfield("Disp32S", types, 1, ARRAY_SIZE (types), lineno); + set_bitfield("Disp32", types, 1, ARRAY_SIZE (types), lineno); } } output_operand_type (table, class, instance, types, ARRAY_SIZE (types), |