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* x86: restore masking of displacement kindsJan Beulich2022-07-041-6/+6
* x86: never set i386_cpu_flags' "unused" fieldJan Beulich2022-03-171-4/+5
* x86: unify CPU flag on/off processingJan Beulich2022-03-171-21/+10
* x86: drop L1OM/K1OM support from gasJan Beulich2022-03-171-7/+1
* x86: assorted IAMCU CPU checking fixesJan Beulich2022-03-171-1/+1
* x86: drop NoAVX insn attributeJan Beulich2022-01-061-1/+0
* Update year range in copyright notice of binutils filesAlan Modra2022-01-021-2/+2
* [PATCH 1/2] Enable Intel AVX512_FP16 instructionsCui,Lili2021-08-051-2/+8
* x86: fold SSE2AVX and their base MMX/SSE templatesJan Beulich2021-03-291-1/+1
* x86: undo Prefix_0X<nn> use in opcode tableJan Beulich2021-03-291-6/+10
* x86: derive opcode encoding space attribute from base opcodeJan Beulich2021-03-291-5/+35
* x86: derive opcode length from opcode valueJan Beulich2021-03-241-17/+15
* x86: derive mandatory prefix attribute from base opcodeJan Beulich2021-03-241-53/+41
* x86: don't use opcode_length to identify pseudo prefixesJan Beulich2021-03-241-2/+1
* x86: re-order two fields of struct insn_templateJan Beulich2021-03-231-4/+4
* x86: split opcode prefix and opcode space representationJan Beulich2021-03-231-0/+1
* x86: fold some prefix related attributes into a single oneJan Beulich2021-03-091-4/+1
* x86: infer operand count of templatesJan Beulich2021-03-031-34/+21
* x86: have preprocessor expand macrosJan Beulich2021-02-161-11/+0
* Segmentation fault i386-genAlan Modra2021-01-261-0/+2
* Update year range in copyright notice of binutils filesAlan Modra2021-01-011-2/+2
* Add AMD znver3 processor supportGanesh Gopalasubramanian2020-10-201-0/+11
* Enhancement for avx-vnni patchCui,Lili2020-10-161-2/+2
* x86: Support Intel AVX VNNIH.J. Lu2020-10-141-0/+6
* x86: Add support for Intel HRESET instructionLili Cui2020-10-141-0/+7
* x86: Support Intel UINTRLili Cui2020-10-141-0/+5
* x86: Remove the prefix byte from non-VEX/EVEX base_opcodeH.J. Lu2020-10-141-3/+52
* x86: Rename VexOpcode to OpcodePrefixH.J. Lu2020-10-131-1/+1
* Add support for Intel TDX instructions.Cui,Lili2020-09-241-0/+5
* Enable support to Intel Keylocker instructionsTerry Guo2020-09-231-0/+10
* x86: Add support for Intel AMX instructionsLili Cui2020-07-101-0/+18
* x86: Add SwapSourcesH.J. Lu2020-07-021-0/+1
* x86: Rename VecSIB to SIB for Intel AMXH.J. Lu2020-06-261-1/+1
* Add support for intel TSXLDTRK instructions$Cui,Lili2020-04-071-0/+5
* Add support for intel SERIALIZE instructionLiliCui2020-04-021-0/+5
* x86: use template for SSE floating point comparison insnsJan Beulich2020-03-091-0/+4
* x86: allow opcode templates to be templatedJan Beulich2020-03-091-46/+267
* x86: drop Rex64 attributeJan Beulich2020-03-061-1/+0
* x86: support VMGEXITJan Beulich2020-03-041-0/+3
* x86: Replace IgnoreSize/DefaultSize with MnemonicSizeH.J. Lu2020-03-031-2/+1
* x86: Remove CpuABM and add CpuPOPCNTH.J. Lu2020-02-171-7/+9
* x86: Don't disable SSE3 when disabling SSE4aH.J. Lu2020-02-161-1/+1
* Re: x86: Don't disable SSE4a when disabling SSE4Alan Modra2020-02-171-2/+2
* x86: Don't disable SSE4a when disabling SSE4H.J. Lu2020-02-161-2/+2
* x86: fix SSE4a dependencies of ".arch .nosse*"Jan Beulich2020-02-131-2/+4
* x86: drop ShortForm attributeJan Beulich2020-02-111-1/+0
* x86: Accept Intel64 only instruction by defaultH.J. Lu2020-02-101-2/+1
* Update year range in copyright notice of binutils filesAlan Modra2020-01-011-2/+2
* x86: consolidate Disp<NN> handling a littleJan Beulich2019-12-271-1/+2
* x86: fold individual Jump* attributes into a single Jump oneJan Beulich2019-11-141-4/+0
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