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* aarch64: Add the RPRFM instructionRichard Sandiford2023-03-301-0/+1
| | | | | | | | | | This patch adds the RPRFM (range prefetch) instruction. It was introduced as part of SME2, but it belongs to the prefetch hint space and so doesn't require any specific ISA flags. The aarch64_rprfmop_array initialiser (deliberately) only fills in the leading non-null elements.
* aarch64: Add new SVE dot-product instructionsRichard Sandiford2023-03-301-1/+2
| | | | | | | This patch adds the SVE FDOT, SDOT and UDOT instructions, which are available when FEAT_SME2 is implemented. The patch also reorders the existing SVE_Zm3_22_INDEX to keep the operands numerically sorted.
* aarch64: Add the SME2 shift instructionsRichard Sandiford2023-03-301-0/+2
| | | | | | | | | | | | | | | There are two instruction formats here: - SQRSHR, SQRSHRU and UQRSHR, which operate on lists of two or four registers. - SQRSHRN, SQRSHRUN and UQRSHRN, which operate on lists of four registers. These are the first SME2 instructions to have immediate operands. The patch makes sure that, when parsing SME2 instructions with immediate operands, the new predicate-as-counter registers are parsed as registers rather than as #-less immediates.
* aarch64: Add the SME2 MLALL and MLSLL instructionsRichard Sandiford2023-03-301-0/+5
| | | | | | | SMLALL, SMLSLL, UMLALL and UMLSLL have the same format. USMLALL and SUMLALL allow the same operand types as those instructions, except that SUMLALL does not have the multi-vector x multi-vector forms (which would be redundant with USMLALL).
* aarch64: Add the SME2 MLAL and MLSL instructionsRichard Sandiford2023-03-301-0/+4
| | | | | | | The {BF,F,S,U}MLAL and {BF,F,S,U}MLSL instructions share the same encoding. They are the first instance of a ZA (as opposed to ZA tile) operand having a range of offsets. As with ZA tiles, the expected range size is encoded in the operand-specific data field.
* aarch64: Add the SME2 FMLA and FMLS instructionsRichard Sandiford2023-03-301-0/+2
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* aarch64: Add the SME2 ADD and SUB instructionsRichard Sandiford2023-03-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | Add support for the SME2 ADD. SUB, FADD and FSUB instructions. SUB and FSUB have the same form as ADD and FADD, except that ADD also has a 2-operand accumulating form. The 64-bit ADD/SUB instructions require FEAT_SME_I16I64 and the 64-bit FADD/FSUB instructions require FEAT_SME_F64F64. These are the first instructions to have tied register list operands, as opposed to tied single registers. The parse_operands change prevents unsuffixed Z registers (width==-1) from being treated as though they had an Advanced SIMD-style suffix (.4s etc.). It means that: Error: expected element type rather than vector type at operand 2 -- `add za\.s\[w8,0\],{z0-z1}' becomes: Error: missing type suffix at operand 2 -- `add za\.s\[w8,0\],{z0-z1}'
* aarch64: Add the SME2 ZT0 instructionsRichard Sandiford2023-03-301-0/+9
| | | | | | | | SME2 adds lookup table instructions for quantisation. They use a new lookup table register called ZT0. LUTI2 takes an unsuffixed SVE vector index of the form Zn[<imm>], which is the first time that this syntax has been used.
* aarch64: Add the SME2 predicate-related instructionsRichard Sandiford2023-03-301-0/+10
| | | | | | | | | | | | | | | | | Implementation-wise, the main things to note here are: - the WHILE* instructions have forms that return a pair of predicate registers. This is the first time that we've had lists of predicate registers, and they wrap around after register 15 rather than after register 31. - the predicate-as-counter WHILE* instructions have a fourth operand that specifies the vector length. We can treat this as an enumeration, except that immediate values aren't allowed. - PEXT takes an unsuffixed predicate index of the form PN<n>[<imm>]. This is the first instance of a vector/predicate index having no suffix.
* aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford2023-03-301-0/+3
| | | | | | | | | | | | | | | SME2 adds LD1 and ST1 variants for lists of 2 and 4 registers. The registers can be consecutive or strided. In the strided case, 2-register lists have a stride of 8, starting at register x0xxx. 4-register lists have a stride of 4, starting at register x00xx. The instructions are predicated on a predicate-as-counter register in the range pn8-pn15. Although we already had register fields with upper bounds of 7 and 15, this is the first plain register operand to have a nonzero lower bound. The patch uses the operand-specific data field to record the minimum value, rather than having separate inserters and extractors for each lower bound. This in turn required adding an extra bit to the field.
* aarch64: Add the SME2 MOVA instructionsRichard Sandiford2023-03-301-0/+8
| | | | | | | | | | | | | | SME2 defines new MOVA instructions for moving multiple registers to and from ZA. As with SME, the instructions are also available through MOV aliases. One notable feature of these instructions (and many other SME2 instructions) is that some register lists must start at a multiple of the list's size. The patch uses the general error "start register out of range" when this constraint isn't met, rather than an error specifically about multiples. This ensures that the error is consistent between these simple consecutive lists and later strided lists, for which the requirements aren't a simple multiple.
* aarch64: Add support for predicate-as-counter registersRichard Sandiford2023-03-301-6/+11
| | | | | | | | | | | | SME2 adds a new format for the existing SVE predicate registers: predicates as counters rather than predicates as masks. In assembly code, operands that interpret predicates as counters are written pn<N> rather than p<N>. This patch adds support for these registers and extends some existing instructions to support them. Since the new forms are just a programmer convenience, there's no need to make them more restrictive than the earlier predicate-as-mask forms.
* aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_arrayRichard Sandiford2023-03-301-1/+1
| | | | | | | SME2 adds various new fields that are similar to AARCH64_OPND_SME_ZA_array, but are distinguished by the size of their offset fields. This patch adds _off4 to the name of the field that we already have.
* aarch64: Add a _10 suffix to FLD_imm3Richard Sandiford2023-03-301-1/+1
| | | | | SME2 adds various new 3-bit immediate fields, so this patch adds an lsb position suffix to the name of the field that we already have.
* aarch64: Regularise FLD_* suffixesRichard Sandiford2023-03-301-16/+16
| | | | | | | | | | | Some FLD_imm* suffixes used a counting scheme such as FLD_immN, FLD_immN_2, FLD_immN_3, etc., while others used the lsb as the suffix. The latter seems more mnemonic, and was a big help in doing the SME2 work. Similarly, the _10 suffix on FLD_SME_size_10 was nonobvious. Presumably it indicated a 2-bit field, but it actually starts in bit 22.
* aarch64: Add an operand class for SVE register listsRichard Sandiford2023-03-301-2/+2
| | | | | | | | | | | | SVE register lists were classified as SVE_REG, since there had been no particular reason to separate them out. However, some SME2 instructions have tied register list operands, and so we need to distinguish registers and register lists when checking whether two operands match. Also, the register list operands used a general error message, even though we already have a dedicated error code for register lists that are the wrong length.
* aarch64: Move ZA range checks to aarch64-opc.cRichard Sandiford2023-03-301-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the range checks on ZA vector select offsets from gas to libopcodes. Doing the checks there means that the error messages contain the expected range. It also fits in better with the error severity scheme, which becomes important later. (This is because out-of-range indices are treated as more severe than syntax errors, on the basis that parsing must have succeeded if we get to the point of checking the completed opcode.) The patch also adds a new check_za_access function for checking ZA accesses. That's a bit over the top for one offset check, but the function becomes more complex with later patches. sme-9-illegal.s checked for an invalid .q suffix using: psel p1, p15, p3.q[w15] but this is doubly invalid because it misses the immediate part of the index. The patch keeps that test but adds another with a zero index, so that .q is the only thing wrong. The aarch64-tbl.h change includes neatening up the backslash positions.
* aarch64: Treat ZA as a registerRichard Sandiford2023-03-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | We already treat the ZA tiles ZA0-ZA15 as registers. This patch does the same for ZA itself. parse_sme_zero_mask can then parse ZA tiles and ZA in the same way, through parsed_type_reg. One important effect of going through parsed_type_reg (in general) is that it allows ZA to take qualifiers. This is necessary for many SME2 instructions. However, to support existing unqualified uses of ZA, parse_reg_with_qual needs to treat the qualiier as optional. Hopefully the net effect is to give better error messages, since now that SME2 makes "za.<T>" valid in some contexts, it might be natural to use it (incorrectly) in ZERO too. While there, the patch also tweaks the error messages for invalid ZA tiles, to try to make some cases more specific. For now, parse_sme_za_array just uses parse_reg, rather than parse_typed_reg/parse_reg_with_qual. A later patch consolidates the parsing further.
* Update year range in copyright notice of binutils filesAlan Modra2023-01-011-1/+1
| | | | | | The newer update-copyright.py fixes file encoding too, removing cr/lf on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
* aarch64: Add support for Common Short Sequence Compression extensionAndre Vieira2022-11-141-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the CSSC extension and its corresponding instructions: ABS, CNT, CTZ, SMAX, UMAX, SMIN, UMIN. gas/ChangeLog: * config/tc-aarch64.c (parse_operands): Handle new operand types. * doc/c-aarch64.texi: Document new extension. * testsuite/gas/aarch64/cssc.d: New test. * testsuite/gas/aarch64/cssc.s: New test. include/ChangeLog: * opcode/aarch64.h (AARCH64_FEATURE_CSSC): New feature Macro. (enum aarch64_opnd): New operand types. (enum aarch64_insn_class): New instruction class. opcodes/ChangeLog: * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-opc.c (operand_general_constraint_met_p): Update for new operand types. (aarch64_print_operand): Likewise. * aarch64-opc.h (enum aarch64_field_kind): Declare FLD_CSSC_imm8 field. * aarch64-tbl.h (aarch64_feature_cssc): Define new feature set. (CSSC): Define new feature set Macro. (CSSC_INSN): Define new instruction type. (aarch64_opcode_table): Add new instructions.
* Arm64: support CLEARBHB aliasJan Beulich2022-10-051-8/+8
| | | | | While the Arm v8 ARM (rev I-a) still doesn't mention this alias, it is (typically via a macro) already in use in kernels and alike.
* Update year range in copyright notice of binutils filesAlan Modra2022-01-021-1/+1
| | | | | | | | | | The result of running etc/update-copyright.py --this-year, fixing all the files whose mode is changed by the script, plus a build with --enable-maintainer-mode --enable-cgen-maint=yes, then checking out */po/*.pot which we don't update frequently. The copy of cgen was with commit d1dd5fcc38ead reverted as that commit breaks building of bfp opcodes files.
* aarch64: Add support for +mopsRichard Sandiford2021-12-021-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for FEAT_MOPS, an Armv8.8-A extension that provides memcpy and memset acceleration instructions. I took the perhaps controversial decision to generate the individual instruction forms using macros rather than list them out individually. This becomes useful with a follow-on patch to check that code follows the correct P/M/E sequence. [https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions?lang=en] include/ * opcode/aarch64.h (AARCH64_FEATURE_MOPS): New macro. (AARCH64_ARCH_V8_8): Make armv8.8-a imply AARCH64_FEATURE_MOPS. (AARCH64_OPND_MOPS_ADDR_Rd): New aarch64_opnd. (AARCH64_OPND_MOPS_ADDR_Rs): Likewise. (AARCH64_OPND_MOPS_WB_Rn): Likewise. opcodes/ * aarch64-asm.h (ins_x0_to_x30): New inserter. * aarch64-asm.c (aarch64_ins_x0_to_x30): New function. * aarch64-dis.h (ext_x0_to_x30): New extractor. * aarch64-dis.c (aarch64_ext_x0_to_x30): New function. * aarch64-tbl.h (aarch64_feature_mops): New feature set. (aarch64_feature_mops_memtag): Likewise. (MOPS, MOPS_MEMTAG, MOPS_INSN, MOPS_MEMTAG_INSN) (MOPS_CPY_OP1_OP2_PME_INSN, MOPS_CPY_OP1_OP2_INSN, MOPS_CPY_OP1_INSN) (MOPS_CPY_INSN, MOPS_SET_OP1_OP2_PME_INSN, MOPS_SET_OP1_OP2_INSN) (MOPS_SET_INSN): New macros. (aarch64_opcode_table): Add MOPS instructions. (aarch64_opcode_table): Add entries for AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn. * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn. (verify_three_different_regs): New function. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. gas/ * doc/c-aarch64.texi: Document +mops. * config/tc-aarch64.c (parse_x0_to_x30): New function. (parse_operands): Handle AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn. (aarch64_features): Add "mops". * testsuite/gas/aarch64/mops.s, testsuite/gas/aarch64/mops.d: New test. * testsuite/gas/aarch64/mops_invalid.s, * testsuite/gas/aarch64/mops_invalid.d, * testsuite/gas/aarch64/mops_invalid.l: Likewise.
* aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus2021-11-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is adding new SVE2 instructions added to support SME extension. The following SVE2 instructions are added by the SME architecture: * PSEL, * REVD, SCLAMP and UCLAMP. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_pred_reg_with_index): New parser. (parse_operands): New parser. * testsuite/gas/aarch64/sme-9-illegal.d: New test. * testsuite/gas/aarch64/sme-9-illegal.l: New test. * testsuite/gas/aarch64/sme-9-illegal.s: New test. * testsuite/gas/aarch64/sme-9.d: New test. * testsuite/gas/aarch64/sme-9.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operand AARCH64_OPND_SME_PnT_Wm_imm. opcodes/ChangeLog: * aarch64-asm.c (aarch64_ins_sme_pred_reg_with_index): New inserter. * aarch64-dis.c (aarch64_ext_sme_pred_reg_with_index): New extractor. * aarch64-opc.c (aarch64_print_operand): Printout of OPND_SME_PnT_Wm_imm. * aarch64-opc.h (enum aarch64_field_kind): New bitfields FLD_SME_Rm, FLD_SME_i1, FLD_SME_tszh, FLD_SME_tszl. * aarch64-tbl.h (OP_SVE_NN_BHSD): New qualifier. (OP_SVE_QMQ): New qualifier. (struct aarch64_opcode): New instructions PSEL, REVD, SCLAMP and UCLAMP. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
* aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus2021-11-171-9/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is adding new SME mode selection and state access instructions: * Add SMSTART and SMSTOP instructions. * Add SVCR system register. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_sm_za): New parser. (parse_operands): New parser. * testsuite/gas/aarch64/sme-8-illegal.d: New test. * testsuite/gas/aarch64/sme-8-illegal.l: New test. * testsuite/gas/aarch64/sme-8-illegal.s: New test. * testsuite/gas/aarch64/sme-8.d: New test. * testsuite/gas/aarch64/sme-8.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operand AARCH64_OPND_SME_SM_ZA. (enum aarch64_insn_class): New instruction classes sme_start and sme_stop. opcodes/ChangeLog: * aarch64-asm.c (aarch64_ins_pstatefield): New inserter. (aarch64_ins_sme_sm_za): New inserter. * aarch64-dis.c (aarch64_ext_imm): New extractor. (aarch64_ext_pstatefield): New extractor. (aarch64_ext_sme_sm_za): New extractor. * aarch64-opc.c (operand_general_constraint_met_p): New pstatefield value for SME instructions. (aarch64_print_operand): Printout for OPND_SME_SM_ZA. (SR_SME): New register SVCR. * aarch64-opc.h (F_REG_IN_CRM): New register endcoding. * aarch64-opc.h (F_IMM_IN_CRM): New immediate endcoding. (PSTATE_ENCODE_CRM): Encode CRm field. (PSTATE_DECODE_CRM): Decode CRm field. (PSTATE_ENCODE_CRM_IMM): Encode CRm immediate field. (PSTATE_DECODE_CRM_IMM): Decode CRm immediate field. (PSTATE_ENCODE_CRM_AND_IMM): Encode CRm and immediate field. * aarch64-tbl.h (struct aarch64_opcode): New SMSTART and SMSTOP instructions. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
* aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus2021-11-171-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is adding new loads and stores defined by SME instructions. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_address): New parser. (parse_sme_za_hv_tiles_operand_with_braces): New parser. (parse_sme_za_array): New parser. (output_operand_error_record): Print error details if present. (parse_operands): Support new operands. * testsuite/gas/aarch64/sme-5-illegal.d: New test. * testsuite/gas/aarch64/sme-5-illegal.l: New test. * testsuite/gas/aarch64/sme-5-illegal.s: New test. * testsuite/gas/aarch64/sme-5.d: New test. * testsuite/gas/aarch64/sme-5.s: New test. * testsuite/gas/aarch64/sme-6-illegal.d: New test. * testsuite/gas/aarch64/sme-6-illegal.l: New test. * testsuite/gas/aarch64/sme-6-illegal.s: New test. * testsuite/gas/aarch64/sme-6.d: New test. * testsuite/gas/aarch64/sme-6.s: New test. * testsuite/gas/aarch64/sme-7-illegal.d: New test. * testsuite/gas/aarch64/sme-7-illegal.l: New test. * testsuite/gas/aarch64/sme-7-illegal.s: New test. * testsuite/gas/aarch64/sme-7.d: New test. * testsuite/gas/aarch64/sme-7.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operands. (enum aarch64_insn_class): Added sme_ldr and sme_str. (AARCH64_OPDE_UNTIED_IMMS): New operand error kind. opcodes/ChangeLog: * aarch64-asm.c (aarch64_ins_sme_za_hv_tiles): New inserter. (aarch64_ins_sme_za_list): New inserter. (aarch64_ins_sme_za_array): New inserter. (aarch64_ins_sme_addr_ri_u4xvl): New inserter. * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): Added ins_sme_za_list, ins_sme_za_array and ins_sme_addr_ri_u4xvl. * aarch64-dis.c (aarch64_ext_sme_za_hv_tiles): New extractor. (aarch64_ext_sme_za_list): New extractor. (aarch64_ext_sme_za_array): New extractor. (aarch64_ext_sme_addr_ri_u4xvl): New extractor. * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): Added ext_sme_za_list, ext_sme_za_array and ext_sme_addr_ri_u4xvl. * aarch64-opc.c (operand_general_constraint_met_p): (aarch64_match_operands_constraint): Handle sme_ldr, sme_str and sme_misc. (aarch64_print_operand): New operands supported. * aarch64-tbl.h (OP_SVE_QUU): New qualifier. (OP_SVE_QZU): New qualifier. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
* aarch64: [SME] Add ZERO instructionPrzemyslaw Wirkus2021-11-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is adding ZERO (a list of 64-bit element ZA tiles) instruction. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_list_of_64bit_tiles): New parser. (parse_operands): Handle OPND_SME_list_of_64bit_tiles. * testsuite/gas/aarch64/sme-4-illegal.d: New test. * testsuite/gas/aarch64/sme-4-illegal.l: New test. * testsuite/gas/aarch64/sme-4-illegal.s: New test. * testsuite/gas/aarch64/sme-4.d: New test. * testsuite/gas/aarch64/sme-4.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operand AARCH64_OPND_SME_list_of_64bit_tiles. opcodes/ChangeLog: * aarch64-opc.c (print_sme_za_list): New printing function. (aarch64_print_operand): Handle OPND_SME_list_of_64bit_tiles. * aarch64-opc.h (enum aarch64_field_kind): New bitfield FLD_SME_zero_mask. * aarch64-tbl.h (struct aarch64_opcode): New ZERO instruction. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
* aarch64: [SME] Add MOV and MOVA instructionsPrzemyslaw Wirkus2021-11-171-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is adding new MOV (alias) and MOVA SME instruction. gas/ChangeLog: * config/tc-aarch64.c (enum sme_hv_slice): new enum. (struct reloc_entry): Added ZAH and ZAV registers. (parse_sme_immediate): Immediate parser. (parse_sme_za_hv_tiles_operand): ZA tile parser. (parse_sme_za_hv_tiles_operand_index): Index parser. (parse_operands): Added ZA tile parser calls. (REGNUMS): New macro. Regs with suffix. (REGSET16S): New macro. 16 regs with suffix. * testsuite/gas/aarch64/sme-2-illegal.d: New test. * testsuite/gas/aarch64/sme-2-illegal.l: New test. * testsuite/gas/aarch64/sme-2-illegal.s: New test. * testsuite/gas/aarch64/sme-2.d: New test. * testsuite/gas/aarch64/sme-2.s: New test. * testsuite/gas/aarch64/sme-2a.d: New test. * testsuite/gas/aarch64/sme-2a.s: New test. * testsuite/gas/aarch64/sme-3-illegal.d: New test. * testsuite/gas/aarch64/sme-3-illegal.l: New test. * testsuite/gas/aarch64/sme-3-illegal.s: New test. * testsuite/gas/aarch64/sme-3.d: New test. * testsuite/gas/aarch64/sme-3.s: New test. * testsuite/gas/aarch64/sme-3a.d: New test. * testsuite/gas/aarch64/sme-3a.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New enums AARCH64_OPND_SME_ZA_HV_idx_src and AARCH64_OPND_SME_ZA_HV_idx_dest. (struct aarch64_opnd_info): New ZA tile vector struct. opcodes/ChangeLog: * aarch64-asm.c (aarch64_ins_sme_za_hv_tiles): New inserter. * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter ins_sme_za_hv_tiles. * aarch64-dis.c (aarch64_ext_sme_za_hv_tiles): New extractor. * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor ext_sme_za_hv_tiles. * aarch64-opc.c (aarch64_print_operand): Handle SME_ZA_HV_idx_src and SME_ZA_HV_idx_dest. * aarch64-opc.h (enum aarch64_field_kind): New enums FLD_SME_size_10, FLD_SME_Q, FLD_SME_V and FLD_SME_Rv. (struct aarch64_operand): Increase fields size to 5. * aarch64-tbl.h (OP_SME_BHSDQ_PM_BHSDQ): New qualifiers aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
* aarch64: [SME] Add SME instructionsPrzemyslaw Wirkus2021-11-171-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch is adding new SME matrix instructions. Please note additional instructions will be added in following patches. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_zada_operand): New parser. * config/tc-aarch64.c (parse_reg_with_qual): New reg parser. * config/tc-aarch64.c (R_ZA): New egister type. (parse_operands): New parser. * testsuite/gas/aarch64/sme-illegal.d: New test. * testsuite/gas/aarch64/sme-illegal.l: New test. * testsuite/gas/aarch64/sme-illegal.s: New test. * testsuite/gas/aarch64/sme.d: New test. * testsuite/gas/aarch64/sme.s: New test. * testsuite/gas/aarch64/sme-f64.d: New test. * testsuite/gas/aarch64/sme-f64.s: New test. * testsuite/gas/aarch64/sme-i64.d: New test. * testsuite/gas/aarch64/sme-i64.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operands AARCH64_OPND_SME_ZAda_2b, AARCH64_OPND_SME_ZAda_3b and AARCH64_OPND_SME_Pm. (enum aarch64_insn_class): New instruction class sme_misc. opcodes/ChangeLog: * aarch64-opc.c (aarch64_print_operand): Print OPND_SME_ZAda_2b and OPND_SME_ZAda_3b operands. (verify_constraints): Handle OPND_SME_Pm. * aarch64-opc.h (enum aarch64_field_kind): New bit fields FLD_SME_ZAda_2b, FLD_SME_ZAda_3b and FLD_SME_Pm. * aarch64-tbl.h (OP_SME_ZADA_PN_PM_ZN_S): New qualifier set. (OP_SME_ZADA_PN_PM_ZN_D): New qualifier. (OP_SME_ZADA_PN_PM_ZN_ZM): New qualifier. (OP_SME_ZADA_S_PM_PM_S_S): New qualifier. (OP_SME_ZADA_D_PM_PM_D_D): New qualifier. (OP_SME_ZADA_S_PM_PM_H_H): New qualifier. (OP_SME_ZADA_S_PM_PM_B_B): New qualifier. (OP_SME_ZADA_D_PM_PM_H_H): New qualifier. (SME_INSN): New instruction macro. (SME_F64_INSN): New instruction macro. (SME_I64_INSN): New instruction macro. (SME_INSNC): New instruction macro. (struct aarch64_opcode): New SME instructions. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
* aarch64: Remove support for CSREKyrylo Tkachov2021-01-111-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes support for the CSRE extension from aarch64 gas/objdump. CSRE (FEAT_CSRE) is part of the Future Architecture Technologies program and at this time Arm is withdrawing this particular feature. The patch removes the system registers and the CSR PDEC instruction. gas/ChangeLog * NEWS: Remove CSRE. * config/tc-aarch64.c (parse_csr_operand): Delete. (parse_operands): Delete handling of AARCH64_OPND_CSRE_CSR. (aarch64_features): Remove csre. * doc/c-aarch64.texi: Remove CSRE. * testsuite/gas/aarch64/csre.d: Delete. * testsuite/gas/aarch64/csre-invalid.s: Likewise. * testsuite/gas/aarch64/csre-invalid.d: Likewise. * testsuite/gas/aarch64/csre_csr.s: Likewise. * testsuite/gas/aarch64/csre_csr.d: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.s: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.l: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.d: Likewise. include/ChangeLog * opcode/aarch64.h (AARCH64_FEATURE_CSRE): Delete. (aarch64_opnd): Delete AARCH64_OPND_CSRE_CSR. opcodes/ChangeLog * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. * aarch64-opc.c (aarch64_print_operand): Delete handling of AARCH64_OPND_CSRE_CSR. * aarch64-tbl.h (aarch64_feature_csre): Delete. (CSRE): Likewise. (_CSRE_INSN): Likewise. (aarch64_opcode_table): Delete csr.
* Update year range in copyright notice of binutils filesAlan Modra2021-01-011-1/+1
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* aarch64: Limit Rt register number for LS64 load/store instructionsPrzemyslaw Wirkus2020-11-091-0/+1
| | | | | | | | | | | | | | | | | Atomic 64-byte load/store instructions limit Rt register number to values matching below condition (register <Xt> number must be even and <= 22): if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED; This patch adds check if Rt fulfills above requirement. For more details regarding atomic 64-byte load/store instruction for Armv8.7 please refer to Arm A64 Instruction set documentation for Armv8-A architecture profile, see document page 157 for load instruction, and pages 414-418 for store instructions of [0]. [0]: https://developer.arm.com/docs/ddi0596/i
* [PATCH][GAS] aarch64: Add atomic 64-byte load/store instructions for Armv8.7Przemyslaw Wirkus2020-11-031-16/+16
| | | | | | | | | | | | | | | | | Armv8.7 architecture introduces the "accelerator extension", aka load/store of 64 bytes. New atomic load/store instructions are: LD64B, ST64B, ST64BV and ST64BV0. This patch adds: + New feature +ls64 to -march command line. + New atomic load/store instructions associated with above feature. For more details regarding atomic 64-byte load/store instruction for Armv8.7 please refer to Arm A64 Instruction set documentation for Armv8-A architecture profile, see document page 157 for load instruction, and pages 414-418 for store instructions of [0]. [0]: https://developer.arm.com/docs/ddi0596/i
* [PATCH][GAS] aarch64: Add WFIT instruction for Armv8.7-aPrzemyslaw Wirkus2020-10-301-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds new to Armv8.7 WFIT instruction which take one operand: WFIT <Xt> Where: <Xt> is 64-bit name of the general-purpose source register, encoded in the "Rd" field. For more details regarding WFIT (Wait For Interrupt with Timeout) instruction for Armv8.7-a please refer to Arm A64 Instruction set documentation for Armv8-A architecture profile, see document pages 570 of [0]. [0]: https://developer.arm.com/docs/ddi0596/i gas/ChangeLog: 2020-10-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Update docs. * testsuite/gas/aarch64/system-5.d: Update test with WFIT insn. * testsuite/gas/aarch64/system-5.s: Update test with WFIT insn. opcodes/ChangeLog: 2020-10-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-tbl.h (struct aarch64_opcode): New instruction WFIT. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
* aarch64: Add CSR PDEC instructionPrzemyslaw Wirkus2020-10-281-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds: + New feature +csre to -march command line. + New instruction CSR PDEC associated with CSRE feature. Please note that CSRE system registers were already upstreamed. This patch should finalize CSRE feature implementation. CSRE feature adds CSR PDEC (Decrements Call stack pointer by the size of a Call stack record) instruction. Although this instruction has operand (PDEC) it's instruction's only operand. PDEC forces instruction field Rt to be set to 0b1111. This results in fixed opcode of the instruction. gas/ChangeLog: 2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Update docs. * config/tc-aarch64.c (parse_csr_operand): New operand parser. (parse_operands): Call to CSR operand parser. * testsuite/gas/aarch64/csre_csr-invalid.d: New test. * testsuite/gas/aarch64/csre_csr-invalid.l: New test. * testsuite/gas/aarch64/csre_csr-invalid.s: New test. * testsuite/gas/aarch64/csre_csr.d: New test. * testsuite/gas/aarch64/csre_csr.s: New test. include/ChangeLog: 2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_CSRE): New -march feature. (enum aarch64_opnd): New CSR instruction field AARCH64_OPND_CSRE_CSR. opcodes/ChangeLog: 2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c (aarch64_print_operand): CSR PDEC operand print-out. * aarch64-tbl.h (CSRE): New CSRE feature handler. (_CSRE_INSN): New CSRE instruction type. (struct aarch64_opcode): New 'csre' entry for a CSRE CLI feature. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
* aarch64: Add WFET instruction for Armv8.7-aPrzemyslaw Wirkus2020-10-281-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds new to Armv8.7 WFET instruction which take one operand: WFET <Xt> Where: <Xt> is 64-bit name of the general-purpose source register, encoded in the "Rd" field. For more details regarding WFET (Wait For Event with Timeout) instruction for Armv8.7-a please refer to Arm A64 Instruction set documentation for Armv8-A architecture profile, see document pages 565 of [0]. [0]: https://developer.arm.com/docs/ddi0596/i gas/ChangeLog: 2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Update docs. * testsuite/gas/aarch64/system-5.d: New test. * testsuite/gas/aarch64/system-5.s: New test. opcodes/ChangeLog: 2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-tbl.h (struct aarch64_opcode): Add new WFET instruction encoding and operand description. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
* aarch64: Add DSB instruction Armv8.7-a variantPrzemyslaw Wirkus2020-10-281-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds new variant (nXS) of DSB memory barrier instruction available in Armv8.7-a. New nXS variant has different encoding in comparison with pre Armv8.7-a DSB memory barrier variant thus new instruction and new operand was added. DSB memory nXS barrier variant specifies the limitation on the barrier operation. Allowed values are: DSB SYnXS|#28 DSB ISHnXS|#24 DSB NSHnXS|#20 DSB OSHnXS|#16 Please note that till now, for barriers, barrier operation was encoded in 4-bit unsigned immediate CRm field (in the range 0 to 15). For DSB memory nXS barrier variant, barrier operation is a 5-bit unsigned assembly instruction immediate, encoded in instruction in two bits CRm<3:2>: CRm<3:2> #imm 00 16 01 20 10 24 11 28 This patch extends current AArch64 barrier instructions with above mapping. Notable patch changes include: + New DSB memory barrier variant encoding for Armv8.7-a. + New operand BARRIER_DSB_NXS for above instruction in order to distinguish between existing and new DSB instruction flavour. + New set of DSB nXS barrier options. + New instruction inserter and extractor map between instruction immediate 5-bit value and 2-bit CRm field of the instruction itself (see FLD_CRm_dsb_nxs). + Regeneration of aarch64-[asm|dis|opc]-2.c files. + Test cases to cover new instruction assembling and disassembling. For more details regarding DSB memory barrier instruction and its Armv8.7-a flavour please refer to Arm A64 Instruction set documentation for Armv8-A architecture profile, see document pages 132-133 of [0]. [0]: https://developer.arm.com/docs/ddi0596/i gas/ChangeLog: 2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Docs update. * config/tc-aarch64.c (parse_operands): Add AARCH64_OPND_BARRIER_DSB_NXS handler. (md_begin): Add content of aarch64_barrier_dsb_nxs_options to aarch64_barrier_opt_hsh hash. * testsuite/gas/aarch64/system-4-invalid.d: New test. * testsuite/gas/aarch64/system-4-invalid.l: New test. * testsuite/gas/aarch64/system-4-invalid.s: New test. * testsuite/gas/aarch64/system-4.d: New test. * testsuite/gas/aarch64/system-4.s: New test. include/ChangeLog: 2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New operand AARCH64_OPND_BARRIER_DSB_NXS. (aarch64_barrier_dsb_nxs_options): Declare DSB nXS options. opcodes/ChangeLog: 2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-asm.c (aarch64_ins_barrier_dsb_nxs): New inserter. * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter ins_barrier_dsb_nx. * aarch64-dis.c (aarch64_ext_barrier_dsb_nxs): New extractor. * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor ext_barrier_dsb_nx. * aarch64-opc.c (aarch64_print_operand): New options table aarch64_barrier_dsb_nxs_options. * aarch64-opc.h (enum aarch64_field_kind): New field name FLD_CRm_dsb_nxs. * aarch64-tbl.h (struct aarch64_opcode): Define DSB nXS barrier Armv8.7-a instruction. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
* aarch64: Add support for Armv8-R DFB aliasAlex Coplan2020-09-081-8/+8
| | | | | | | | | | | | | | | | | | | | | | | This adds support for the DFB alias introduced in Armv8-R AArch64. gas/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * testsuite/gas/aarch64/dfb.d: New test. * testsuite/gas/aarch64/dfb.s: Input. opcodes/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * aarch64-tbl.h (aarch64_feature_v8_r): New. (ARMV8_R): New. (V8_R_INSN): New. (aarch64_opcode_table): Add dfb. * aarch64-opc-2.c: Regenerate. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate.
* AArch64: add GAS support for UDF instructionAlex Coplan2020-04-301-26/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | binutils * testsuite/binutils-all/aarch64/in-order-all.d: Update to use new disassembly. * testsuite/binutils-all/aarch64/out-of-order-all.d: Likewise. ld/ * testsuite/ld-aarch64/erratum843419_tls_ie.d: Use udf in disassembly. * testsuite/ld-aarch64/farcall-b-section.d: Likewise. * testsuite/ld-aarch64/farcall-back.d: Likewise. * testsuite/ld-aarch64/farcall-bl-section.d: Likewise. gas/ * config/tc-aarch64.c (fix_insn): Implement for AARCH64_OPND_UNDEFINED. (parse_operands): Implement for AARCH64_OPND_UNDEFINED. * testsuite/gas/aarch64/udf.s: New. * testsuite/gas/aarch64/udf.d: New. * testsuite/gas/aarch64/udf-invalid.s: New. * testsuite/gas/aarch64/udf-invalid.l: New. * testsuite/gas/aarch64/udf-invalid.d: New. include * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_UNDEFINED. opcodes * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2. * aarch64-opc.c (fields): Add entry for FLD_imm16_2. (operand_general_constraint_met_p): validate AARCH64_OPND_UNDEFINED. * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry for FLD_imm16_2. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
* [AArch64, Binutils] Add missing TSB instructionSudakshina Das2020-04-201-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements the TSB instructions: https://developer.arm.com/docs/ddi0596/f/base-instructions-alphabetic-order/ tsb-csync-trace-synchronization-barrier Since TSB and PSB both use the same (and only) argument "CSYNC", this patch reuses it for TSB. However, the same argument would imply different value for CRm:Op2 which are anyway fixed values, so I have diverted the inserter/extracter function to dummy versions instead of the "hint" version. The operand checker part still uses the existing infratructure for AARCH64_OPND_BARRIER_PSB to make sure the operand is parsed correctly. gas/ChangeLog: 2020-04-20 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_barrier_psb): Update error messages to include TSB. * testsuite/gas/aarch64/system-2.d: Update -march and new tsb tests. * testsuite/gas/aarch64/system-2.s: Add new tsb tests. * testsuite/gas/aarch64/system.d: Update. opcodes/ChangeLog: 2020-04-20 Sudakshina Das <sudi.das@arm.com> * aarch64-asm.c (aarch64_ins_none): New. * aarch64-asm.h (ins_none): New declaration. * aarch64-dis.c (aarch64_ext_none): New. * aarch64-dis.h (ext_none): New declaration. * aarch64-opc.c (aarch64_print_operand): Update case for AARCH64_OPND_BARRIER_PSB. * aarch64-tbl.h (aarch64_opcode_table): Add tsb. (AARCH64_OPERANDS): Update inserter/extracter for AARCH64_OPND_BARRIER_PSB to use new dummy functions. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
* [AArch64, Binutils] Make hint space instructions valid for Armv8-aSudakshina Das2020-04-201-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a few instruction in AArch64 that are in the HINT space. Any of these instructions should be accepted by the assembler/disassembler at any architecture version. This patch fixes the existing instructions that are not behaving accordingly. I have used all of the instructions mentioned in the following to make the changes: https://developer.arm.com/docs/ddi0596/f/base-instructions-alphabetic-order/ hint-hint-instruction gas/ChangeLog: 2020-04-20 Sudakshina Das <sudi.das@arm.com> * testsuite/gas/aarch64/bti.d: Update -march option. * testsuite/gas/aarch64/illegal-bti.d: Remove. * testsuite/gas/aarch64/illegal-bti.l: Remove. * testsuite/gas/aarch64/illegal-ras-1.l: Remove esb. * testsuite/gas/aarch64/illegal-ras-1.s: Remove esb. opcodes/ChangeLog: 2020-04-20 Sudakshina Das <sudi.das@arm.com> * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove. (aarch64_feature_ras, RAS): Likewise. (aarch64_feature_stat_profile, STAT_PROFILE): Likewise. (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716, autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz, autibsp to be CORE_INSN. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
* AArch64: Fix cfinv disassembly issuesTamar Christina2020-01-271-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the preferred disassembly for cfinv. The Armv8.4-a instruction overlaps with the possible encoding space for msr. This because msr allows you to use unallocated encoding space using the general sA_B_cC_cD_E form. However when an encoding does become allocated then we need to ensure that it's used as the preferred disassembly. The problem with cfinv is that its mask has all bits sets because it has no arguments. This causes issues for the Alias resolver in gas as it uses the mask to build alias graph. In this case it can't do it since it thinks almost everything would alias with cfinv. So instead we can only fix this by moving cfinv before msr. gas/ChangeLog: PR 25403 * testsuite/gas/aarch64/armv8_4-a.d: Add cfinv. * testsuite/gas/aarch64/armv8_4-a.s: Likewise. opcodes/ChangeLog: PR 25403 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv. * aarch64-asm-2.c: Regenerate * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise.
* Update year range in copyright notice of binutils filesAlan Modra2020-01-011-1/+1
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* [binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson2019-11-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces the Matrix Multiply (Int8, F32, F64) extensions to the aarch64 backend. The following instructions are added: {s/u}mmla, usmmla, {us/su}dot, fmmla, ld1rob, ld1roh, d1row, ld1rod, uzip{1/2}, trn{1/2}. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * config/tc-aarch64.c: Add new arch fetures to suppport the mm extension. (parse_operands): Add new operand. * testsuite/gas/aarch64/i8mm.s: New test. * testsuite/gas/aarch64/i8mm.d: New test. * testsuite/gas/aarch64/f32mm.s: New test. * testsuite/gas/aarch64/f32mm.d: New test. * testsuite/gas/aarch64/f64mm.s: New test. * testsuite/gas/aarch64/f64mm.d: New test. * testsuite/gas/aarch64/sve-movprfx-mm.s: New test. * testsuite/gas/aarch64/sve-movprfx-mm.d: New test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_I8MM): New. (AARCH64_FEATURE_F32MM): New. (AARCH64_FEATURE_F64MM): New. (AARCH64_OPND_SVE_ADDR_RI_S4x32): New. (enum aarch64_insn_class): Add new instruction class "aarch64_misc" for instructions that do not require special handling. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve, aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm, aarch64_feature_f64mm): New feature sets. (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN, F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply instructions. (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set macros. (QL_MMLA64, OP_SVE_SBB): New qualifiers. (OP_SVE_QQQ): New qualifier. (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC, F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support the movprfx constraint. (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32. (aarch64_opcode_table): Define new instructions smmla, ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod uzip{1/2}, trn{1/2}. * aarch64-opc.c (operand_general_constraint_met_p): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32. (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32. * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode): Account for new instructions. * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new S4x32 operand. * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand. Regression tested on arm-none-eabi. Is it ok for trunk? Regards, Mihail
* Modify the ARNM assembler to accept the omission of the immediate argument ↵Delia Burduv2019-10-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | for the writeback form of the LDRAA and LDRAB mnemonics This is a shorthand for the immediate argument being 0, as described here: https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order/ldraa-ldrab-load-register-with-pointer-authentication This is because the instructions still have a use with an immediate argument of 0, unlike loads without the PAC functionality. Currently, the mnemonics are LDRAA Xt, [Xn, #<simm10>]! LDRAB Xt, [Xn, #<simm10>]! After this patch they become LDRAA Xt, [Xn {, #<simm10>}]! LDRAB Xt, [Xn {, #<simm10>}]! gas * config/tc-aarch64.c (parse_address_main): Accept the omission of the immediate argument for ldraa and ldrab as a shorthand for the immediate being 0. * testsuite/gas/aarch64/ldraa-ldrab-no-offset.d: New test. * testsuite/gas/aarch64/ldraa-ldrab-no-offset.s: New test. * testsuite/gas/aarch64/illegal-ldraa.s: Modified to accept the writeback form with no offset. * testsuite/gas/aarch64/illegal-ldraa.s: Removed missing offset error. opcodes * aarch64-opc.c (print_immediate_offset_address): Don't print the immediate for the writeback form of ldraa/ldrab if it is 0. * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10. * aarch64-opc-2.c: Regenerated.
* [binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand.Matthew Malcomson2019-05-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New operand describes a shift-left immediate encoded in bits 22:20-19:18-16 where UInt(bits) - esize == shift. This operand is useful for instructions like sshllb. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_SHLIMM_UNPRED_22 operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_SHLIMM_UNPRED_22 operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_SHLIMM_UNPRED_22. (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22 operand.
* [binutils][aarch64] New SVE_Zm4_11_INDEX operand.Matthew Malcomson2019-05-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This includes defining a new single bit field SVE_i2h at position 20. SVE_Zm4_11_INDEX handles indexed Zn registers where the index is encoded in bits 20:11 and the register is chosed from range z0-z15 in bits 19-16. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_Zm4_11_INDEX operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm4_11_INDEX operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_Zm4_11_INDEX. (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX. (fields): Handle SVE_i2h field. * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
* [binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.Matthew Malcomson2019-05-091-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Include a new iclass to extract the variant from the most significant 3 bits of this operand. Instructions such as rshrnb include a constant shift amount as an operand, where the most significant three bits of this operand determine what size elements the instruction is operating on. The new SVE_SHRIMM_UNPRED_22 operand denotes this constant encoded in bits 22:20-19:18-16 while the new sve_shift_tsz_hsd iclass denotes that the SVE qualifier is encoded in bits 22:20-19. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_SHRIMM_UNPRED_22 operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22 operand. (enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-asm.c (aarch64_ins_sve_shrimm): (aarch64_encode_variant_using_iclass): Handle sve_shift_tsz_hsd iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_shift_tsz_hsd iclass decode. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_SHRIMM_UNPRED_22. (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22 operand.
* [binutils][aarch64] New SVE_ADDR_ZX operand.Matthew Malcomson2019-05-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add AARCH64_OPND_SVE_ADDR_ZX operand that allows a vector of addresses in a Zn register, offset by an Xm register. This is used with scatter/gather SVE2 instructions. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (REG_ZR): Macro specifying zero register. (parse_address_main): Account for new addressing mode [Zn.S, Xm]. (parse_operands): Handle new SVE_ADDR_ZX operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_ADDR_ZX operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_ADDR_ZX. (aarch64_print_operand): Add printing for SVE_ADDR_ZX. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
* [binutils][aarch64] New SVE_Zm3_11_INDEX operand.Matthew Malcomson2019-05-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce new operand SVE_Zm3_11_INDEX that indicates a register between z0-z7 stored in bits 18-16 and an index stored in bits 20-19:11. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_Zm3_11_INDEX operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm3_11_INDEX operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_Zm3_11_INDEX. (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX. (fields): Handle SVE_i3l and SVE_i3h2 fields. * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2 fields. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
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