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| author | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2020-11-09 11:09:12 +0000 |
|---|---|---|
| committer | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2020-11-09 11:19:44 +0000 |
| commit | 8edca81ece5df534c1cdd1f8362e7b5b9b090cfa (patch) | |
| tree | 7e07cdc4b08f84ca60406cc67afd31eaa71c8bf3 /opcodes/aarch64-opc-2.c | |
| parent | a76bf0e55d84e8529a337cad278814ba2e30d3af (diff) | |
| download | binutils-gdb-8edca81ece5df534c1cdd1f8362e7b5b9b090cfa.tar.gz | |
aarch64: Limit Rt register number for LS64 load/store instructions
Atomic 64-byte load/store instructions limit Rt register number to
values matching below condition (register <Xt> number must be even
and <= 22):
if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED;
This patch adds check if Rt fulfills above requirement.
For more details regarding atomic 64-byte load/store instruction for
Armv8.7 please refer to Arm A64 Instruction set documentation for
Armv8-A architecture profile, see document page 157 for load
instruction, and pages 414-418 for store instructions of [0].
[0]: https://developer.arm.com/docs/ddi0596/i
Diffstat (limited to 'opcodes/aarch64-opc-2.c')
| -rw-r--r-- | opcodes/aarch64-opc-2.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index e3d47b4bb5e..f5c67095b99 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -30,6 +30,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_INT_REG, "Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer register"}, {AARCH64_OPND_CLASS_INT_REG, "Rt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"}, {AARCH64_OPND_CLASS_INT_REG, "Rt2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt2}, "an integer register"}, + {AARCH64_OPND_CLASS_INT_REG, "Rt_LS64", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"}, {AARCH64_OPND_CLASS_INT_REG, "Rt_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer or stack pointer register"}, {AARCH64_OPND_CLASS_INT_REG, "Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "an integer register"}, {AARCH64_OPND_CLASS_INT_REG, "Ra", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "an integer register"}, |