AArch64: Fix cfinv disassembly issues

This fixes the preferred disassembly for cfinv.  The Armv8.4-a instruction
overlaps with the possible encoding space for msr.  This because msr allows you
to use unallocated encoding space using the general sA_B_cC_cD_E form.

However when an encoding does become allocated then we need to ensure that it's
used as the preferred disassembly.  The problem with cfinv is that its mask has
all bits sets because it has no arguments.

This causes issues for the Alias resolver in gas as it uses the mask to build
alias graph.  In this case it can't do it since it thinks almost everything
would alias with cfinv.  So instead we can only fix this by moving cfinv before
msr.

gas/ChangeLog:

	PR 25403
	* testsuite/gas/aarch64/armv8_4-a.d: Add cfinv.
	* testsuite/gas/aarch64/armv8_4-a.s: Likewise.

opcodes/ChangeLog:

	PR 25403
	* aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
	* aarch64-asm-2.c: Regenerate
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.

1 files changed, 8 insertions, 8 deletions

diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 1f8b5943efa..99378ab6953 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -309,17 +309,17 @@ static const unsigned op_enum_table [] =
   391,
   413,
   415,
-  1258,
-  1263,
-  1256,
-  1255,
   1259,
-  1266,
-  1268,
+  1264,
+  1257,
+  1256,
+  1260,
+  1267,
   1269,
-  1265,
-  1271,
   1270,
+  1266,
+  1272,
+  1271,
   131,
 };