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path: root/opcodes/aarch64-asm-2.c
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* aarch64: Add the RPRFM instructionRichard Sandiford2023-03-301-68/+69
* aarch64: Add new SVE dot-product instructionsRichard Sandiford2023-03-301-34/+35
* aarch64: Add the SME2 shift instructionsRichard Sandiford2023-03-301-10/+13
* aarch64: Add the SME2 MLALL and MLSLL instructionsRichard Sandiford2023-03-301-15/+20
* aarch64: Add the SME2 MLAL and MLSL instructionsRichard Sandiford2023-03-301-16/+20
* aarch64: Add the SME2 FMLA and FMLS instructionsRichard Sandiford2023-03-301-8/+10
* aarch64: Add the SME2 ADD and SUB instructionsRichard Sandiford2023-03-301-25/+26
* aarch64: Add the SME2 ZT0 instructionsRichard Sandiford2023-03-301-8/+17
* aarch64: Add the SME2 predicate-related instructionsRichard Sandiford2023-03-301-20/+31
* aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford2023-03-301-20/+24
* aarch64: Add the SME2 MOVA instructionsRichard Sandiford2023-03-301-12/+22
* aarch64: Add support for predicate-as-counter registersRichard Sandiford2023-03-301-117/+122
* Update year range in copyright notice of binutils filesAlan Modra2023-01-011-1/+1
* aarch64: Add support for Common Short Sequence Compression extensionAndre Vieira2022-11-141-0/+2
* Arm64: support CLEARBHB aliasJan Beulich2022-10-051-105/+106
* Update year range in copyright notice of binutils filesAlan Modra2022-01-021-1/+1
* aarch64: Add support for +mopsRichard Sandiford2021-12-021-0/+4
* aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus2021-11-171-2/+4
* aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus2021-11-171-149/+151
* aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus2021-11-171-36/+42
* aarch64: [SME] Add ZERO instructionPrzemyslaw Wirkus2021-11-171-1/+2
* aarch64: [SME] Add MOV and MOVA instructionsPrzemyslaw Wirkus2021-11-171-3/+6
* aarch64: [SME] Add SME instructionsPrzemyslaw Wirkus2021-11-171-2/+5
* Use bool in opcodesAlan Modra2021-03-311-1/+1
* aarch64: Remove support for CSREKyrylo Tkachov2021-01-111-124/+124
* Update year range in copyright notice of binutils filesAlan Modra2021-01-011-1/+1
* aarch64: Limit Rt register number for LS64 load/store instructionsPrzemyslaw Wirkus2020-11-091-80/+81
* [PATCH][GAS] aarch64: Add atomic 64-byte load/store instructions for Armv8.7Przemyslaw Wirkus2020-11-031-343/+343
* [PATCH][GAS] aarch64: Add WFIT instruction for Armv8.7-aPrzemyslaw Wirkus2020-10-301-89/+92
* aarch64: Add CSR PDEC instructionPrzemyslaw Wirkus2020-10-281-122/+122
* aarch64: Add WFET instruction for Armv8.7-aPrzemyslaw Wirkus2020-10-281-89/+92
* aarch64: Add DSB instruction Armv8.7-a variantPrzemyslaw Wirkus2020-10-281-141/+146
* aarch64: Add support for Armv8-R DFB aliasAlex Coplan2020-09-081-98/+99
* AArch64: add GAS support for UDF instructionAlex Coplan2020-04-301-384/+385
* [AArch64, Binutils] Add missing TSB instructionSudakshina Das2020-04-201-102/+104
* [AArch64, Binutils] Make hint space instructions valid for Armv8-aSudakshina Das2020-04-201-109/+109
* AArch64: Fix cfinv disassembly issuesTamar Christina2020-01-271-87/+87
* Update year range in copyright notice of binutils filesAlan Modra2020-01-011-1/+1
* [binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson2019-11-071-38/+39
* [binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand.Matthew Malcomson2019-05-091-11/+12
* [binutils][aarch64] New SVE_Zm4_11_INDEX operand.Matthew Malcomson2019-05-091-7/+8
* [binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.Matthew Malcomson2019-05-091-10/+11
* [binutils][aarch64] New SVE_ADDR_ZX operand.Matthew Malcomson2019-05-091-33/+34
* [binutils][aarch64] New SVE_Zm3_11_INDEX operand.Matthew Malcomson2019-05-091-7/+8
* [binutils][aarch64] Introduce SVE_IMM_ROT3 operand.Matthew Malcomson2019-05-091-19/+20
* [BINUTILS, AArch64] Enable Transactional Memory ExtensionSudakshina Das2019-05-011-137/+138
* [BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructionsSudakshina Das2019-04-111-76/+77
* [BINUTILS, AArch64, 1/2] Add new LDGM/STGM instructionSudakshina Das2019-04-111-295/+295
* AArch64: Add new STZGM instruction for Armv8.5-A Memory Tagging Extension.Sudi Das2019-01-251-316/+316
* AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Exte...Sudi Das2019-01-251-348/+346
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