aarch64: Add the SME2 ADD and SUB instructions

Add support for the SME2 ADD. SUB, FADD and FSUB instructions.
SUB and FSUB have the same form as ADD and FADD, except that
ADD also has a 2-operand accumulating form.

The 64-bit ADD/SUB instructions require FEAT_SME_I16I64 and the
64-bit FADD/FSUB instructions require FEAT_SME_F64F64.

These are the first instructions to have tied register list
operands, as opposed to tied single registers.

The parse_operands change prevents unsuffixed Z registers (width==-1)
from being treated as though they had an Advanced SIMD-style suffix
(.4s etc.).  It means that:

  Error: expected element type rather than vector type at operand 2 -- `add za\.s\[w8,0\],{z0-z1}'

becomes:

  Error: missing type suffix at operand 2 -- `add za\.s\[w8,0\],{z0-z1}'

1 files changed, 26 insertions, 25 deletions

diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index cdc9e465d13..5dba041483c 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -667,12 +667,13 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 203:
     case 209:
     case 212:
-    case 222:
+    case 216:
     case 223:
-    case 230:
+    case 224:
     case 231:
     case 232:
     case 233:
+    case 234:
       return aarch64_ins_regno (self, info, code, inst, errors);
     case 15:
       return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -684,7 +685,7 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 33:
     case 34:
     case 35:
-    case 256:
+    case 257:
       return aarch64_ins_reglane (self, info, code, inst, errors);
     case 36:
       return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -729,13 +730,13 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 192:
     case 193:
     case 194:
-    case 236:
-    case 250:
+    case 237:
     case 251:
-    case 253:
-    case 255:
-    case 260:
+    case 252:
+    case 254:
+    case 256:
     case 261:
+    case 262:
       return aarch64_ins_imm (self, info, code, inst, errors);
     case 44:
     case 45:
@@ -804,8 +805,8 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 107:
       return aarch64_ins_prfop (self, info, code, inst, errors);
     case 108:
-    case 252:
-    case 254:
+    case 253:
+    case 255:
       return aarch64_ins_none (self, info, code, inst, errors);
     case 109:
       return aarch64_ins_hint (self, info, code, inst, errors);
@@ -896,48 +897,48 @@ aarch64_insert_operand (const aarch64_operand *self,
       return aarch64_ins_sve_index (self, info, code, inst, errors);
     case 211:
     case 213:
-    case 229:
+    case 230:
       return aarch64_ins_sve_reglist (self, info, code, inst, errors);
     case 214:
     case 215:
-    case 216:
     case 217:
     case 218:
     case 219:
-    case 228:
-      return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
     case 220:
+    case 229:
+      return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
     case 221:
+    case 222:
       return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
-    case 224:
-    case 226:
-    case 237:
-      return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
     case 225:
     case 227:
+    case 238:
+      return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
+    case 226:
+    case 228:
       return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
-    case 234:
     case 235:
-    case 244:
+    case 236:
     case 245:
     case 246:
     case 247:
     case 248:
     case 249:
+    case 250:
       return aarch64_ins_simple_index (self, info, code, inst, errors);
-    case 238:
     case 239:
     case 240:
-      return aarch64_ins_sme_za_array (self, info, code, inst, errors);
     case 241:
-      return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
+      return aarch64_ins_sme_za_array (self, info, code, inst, errors);
     case 242:
-      return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
+      return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
     case 243:
+      return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
+    case 244:
       return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
-    case 257:
     case 258:
     case 259:
+    case 260:
       return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
     default: assert (0); abort ();
     }