diff options
| author | Lionel Landwerlin <lionel.g.landwerlin@intel.com> | 2022-07-18 12:27:53 +0300 |
|---|---|---|
| committer | Marge Bot <emma+marge@anholt.net> | 2022-08-24 17:51:40 +0000 |
| commit | 37b3601052c35ebce78a14a34d0ae0095890bce3 (patch) | |
| tree | f9eadee761a062be0d0fb25133968f7c7eec3e44 /src/intel/compiler/brw_fs_generator.cpp | |
| parent | 3c6fa2703dad46a5026cc3993224feff0f106745 (diff) | |
| download | mesa-37b3601052c35ebce78a14a34d0ae0095890bce3.tar.gz | |
intel/fs: switch register allocation spilling to use LSC on Gfx12.5+
v2: drop the hardcoded inst->mlen=1 (Rohan)
v3: Move back to LOAD/STORE messages (limited to SIMD16 for LSC)
v4: Also use 4 GRFs transpose loads for fills (Curro)
v5: Reduce amount of needed register to build per lane offsets (Curro)
Drop some now useless SIMD32 code
Unify unspill code
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17555>
Diffstat (limited to 'src/intel/compiler/brw_fs_generator.cpp')
| -rw-r--r-- | src/intel/compiler/brw_fs_generator.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index e8c45b4e59c..62f5cb51fe1 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -335,13 +335,14 @@ fs_generator::generate_send(fs_inst *inst, uint32_t ex_desc_imm = inst->ex_desc | brw_message_ex_desc(devinfo, inst->ex_mlen); - if (ex_desc.file != BRW_IMMEDIATE_VALUE || ex_desc.ud || ex_desc_imm) { + if (ex_desc.file != BRW_IMMEDIATE_VALUE || ex_desc.ud || ex_desc_imm || + inst->send_ex_desc_scratch) { /* If we have any sort of extended descriptor, then we need SENDS. This * also covers the dual-payload case because ex_mlen goes in ex_desc. */ brw_send_indirect_split_message(p, inst->sfid, dst, payload, payload2, desc, desc_imm, ex_desc, ex_desc_imm, - inst->eot); + inst->send_ex_desc_scratch, inst->eot); if (inst->check_tdr) brw_inst_set_opcode(p->isa, brw_last_inst, devinfo->ver >= 12 ? BRW_OPCODE_SENDC : BRW_OPCODE_SENDSC); |