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path: root/src/intel/compiler/brw_fs_generator.cpp
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* intel/compiler: report max dispatch width statisticLionel Landwerlin2023-03-211-0/+1
* intel/compiler: Add swsb_stall debug optionSagar Ghuge2023-03-101-0/+9
* intel/eu: Simplify brw_F32TO16 and brw_F16TO32Kenneth Graunke2023-03-091-2/+0
* intel/fs: Move packHalf2x16 handling to lower_pack()Kenneth Graunke2023-03-091-53/+0
* intel/fs: report max register pressure in shader statsLionel Landwerlin2023-03-081-0/+1
* intel/fs: use generated workaround helpers for Wa_14010017096Mark Janes2023-03-071-1/+2
* intel/compiler: Use SHADER_OPCODE_SEND for PI messagesJason Ekstrand2023-02-061-43/+0
* intel/fs: drop FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GFX7Lionel Landwerlin2023-01-261-67/+0
* intel/fs: Always use integer types for indirect MOVsJason Ekstrand2022-09-281-0/+23
* intel/fs: switch register allocation spilling to use LSC on Gfx12.5+Lionel Landwerlin2022-08-241-2/+3
* intel/compiler: Delete unused Gfx8+ code in brw_find_live_channel()Kenneth Graunke2022-08-021-24/+4
* intel/fs: Remove non-_LOGICAL URB messagesIan Romanick2022-07-081-69/+0
* intel/compiler: Introduce a new brw_isa_info structureKenneth Graunke2022-06-301-7/+7
* intel/fs: Add missing synchronization for WaW dependencyIan Romanick2022-06-171-0/+2
* intel: Only set VectorMaskEnable when neededJason Ekstrand2022-05-271-3/+9
* intel/compiler: Move spill/fill tracking to the register allocatorKenneth Graunke2022-05-251-23/+21
* intel/fs: Better handle constant sources of FS_OPCODE_PACK_HALF_2x16_SPLITIan Romanick2022-04-071-10/+16
* intel/compiler: Implement nir_intrinsic_last_invocationKenneth Graunke2022-03-261-1/+13
* intel/fs: Add Wa_22013689345Sagar Ghuge2022-03-171-0/+1
* intel/fs: Assert that old pull-const code is not used if devinfo->has_lscJordan Justen2022-02-091-0/+1
* intel/fs: rework dss_id opcode into generic opcodeLionel Landwerlin2022-02-081-17/+6
* intel/fs: Perform 64-bit CLUSTER_BROADCAST lowering in the lower_regioning pass.Francisco Jerez2022-01-251-29/+4
* intel/fs: Honor strided source regions specified by the IR for CLUSTER_BROADC...Francisco Jerez2022-01-251-2/+4
* intel/fs: Perform 64-bit SEL_EXEC lowering in the lower_regioning pass.Francisco Jerez2022-01-251-19/+6
* intel/fs: Perform 64-bit SHUFFLE lowering in the lower_regioning pass.Francisco Jerez2022-01-251-44/+5
* intel/fs: Fix destination suboffset calculations for non-trivial strides in S...Francisco Jerez2022-01-251-2/+2
* intel/fs: Take into account region strides during SIMD lowering decision of S...Francisco Jerez2022-01-251-2/+2
* intel/fs: Use HF as destination type for F32TOF16 in fquantize2f16Ian Romanick2021-12-151-1/+3
* intel/fs,vec4: Drop prog_data binding tablesJason Ekstrand2021-12-101-11/+1
* intel/fs,vec4: Drop support for shader timeJason Ekstrand2021-12-101-45/+0
* intel/compiler: Set correct return format for brw_SAMPLESagar Ghuge2021-11-221-1/+4
* intel: move away from booleans to identify platformsLionel Landwerlin2021-11-081-7/+8
* intel/compiler: add missing line returns to logsLionel Landwerlin2021-10-051-1/+1
* intel/compiler: Basic support for DP4A instructionIan Romanick2021-08-241-0/+5
* intel/compiler: Add id parameter to shader_debug_log callbackIan Romanick2021-08-011-13/+13
* intel/compiler: Add support for ternary add instruction on XeHPSagar Ghuge2021-07-161-0/+5
* intel/fs: Implement Wa_14013745556 on TGL+.Francisco Jerez2021-06-231-0/+17
* intel/fs: Fix synchronization of accumulator-clearing W/A move on TGL+.Francisco Jerez2021-06-231-3/+6
* intel/fs: Add support for compiling bindless shaders with resume shadersJason Ekstrand2021-06-221-0/+18
* intel: simplify is_haswell checks, part 1Marcin Ślusarz2021-05-171-9/+9
* intel/fs: Stop using brw_dp_read/write_desc in Gen7+ only codeJason Ekstrand2021-05-021-8/+6
* intel/compiler: add support for fragment coordinate with coarse pixelsLionel Landwerlin2021-05-021-2/+16
* intel/compiler: handle coarse pixel in render target writes descriptorsLionel Landwerlin2021-05-021-0/+3
* intel: Rename gen_device prefix to intel_deviceAnuj Phogat2021-04-201-4/+4
* intel/fs: End computer shader with message gateway on XeHP.Jordan Justen2021-04-161-2/+7
* intel/compiler: Lower integer division on XeHP.Francisco Jerez2021-04-161-0/+1
* intel/fs: Use CHV/BXT implementation of 64-bit MOV_INDIRECT on XeHP+.Francisco Jerez2021-04-161-1/+1
* Convert most remaining free-form fall-through comments to FALLTHROUGHMichel Dänzer2021-04-151-1/+1
* intel: Rename GEN:BUG:### to Wa_###Anuj Phogat2021-04-021-1/+1
* intel: Rename GENx keyword to GFXxAnuj Phogat2021-04-021-5/+5
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