diff options
| author | Marek Olšák <marek.olsak@amd.com> | 2022-10-21 15:10:40 -0400 |
|---|---|---|
| committer | Marge Bot <emma+marge@anholt.net> | 2023-04-06 15:00:53 +0000 |
| commit | d3b03fedd8cc689a0d1571bc1f5a5aa52371a304 (patch) | |
| tree | 4e57cfa5112610f6b070841bde9ac52499a45eb5 /src/amd/registers | |
| parent | 46639eb05629d4d70314aec57b93feb0af20f3fa (diff) | |
| download | mesa-d3b03fedd8cc689a0d1571bc1f5a5aa52371a304.tar.gz | |
amd: add initial code for gfx940
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>
Diffstat (limited to 'src/amd/registers')
| -rw-r--r-- | src/amd/registers/makeregheader.py | 1 | ||||
| -rw-r--r-- | src/amd/registers/parse_kernel_headers.py | 12 |
2 files changed, 12 insertions, 1 deletions
diff --git a/src/amd/registers/makeregheader.py b/src/amd/registers/makeregheader.py index db5def95cac..e0c943736b9 100644 --- a/src/amd/registers/makeregheader.py +++ b/src/amd/registers/makeregheader.py @@ -46,6 +46,7 @@ CHIPS = [ Object(name='gfx8', disambiguation='GFX8'), Object(name='gfx81', disambiguation='GFX81'), Object(name='gfx9', disambiguation='GFX9'), + Object(name='gfx940', disambiguation='GFX940'), Object(name='gfx10', disambiguation='GFX10'), Object(name='gfx103', disambiguation='GFX103'), Object(name='gfx11', disambiguation='GFX11'), diff --git a/src/amd/registers/parse_kernel_headers.py b/src/amd/registers/parse_kernel_headers.py index f3a43864950..d10e475ac00 100644 --- a/src/amd/registers/parse_kernel_headers.py +++ b/src/amd/registers/parse_kernel_headers.py @@ -36,6 +36,12 @@ gfx_levels = { 'asic_reg/gc/gc_9_2_1_sh_mask.h', 'vega10_enum.h', ], + 'gfx940': [ + [0x00002000, 0x0000A000, 0, 0, 0], # IP_BASE GC_BASE + 'asic_reg/gc/gc_9_4_3_offset.h', + 'asic_reg/gc/gc_9_4_3_sh_mask.h', + 'vega10_enum.h', + ], 'gfx10': [ [0x00001260, 0x0000A000, 0x02402C00, 0, 0], # IP_BASE GC_BASE 'asic_reg/gc/gc_10_1_0_offset.h', @@ -73,7 +79,8 @@ def register_filter(gfx_level, name, offset, already_added): umd_ranges = [0xB] # Gfx context, uconfig, and perf counter registers - umd_ranges += [0x28, 0x30, 0x31, 0x34, 0x35, 0x36, 0x37] + if gfx_level != 'gfx940': + umd_ranges += [0x28, 0x30, 0x31, 0x34, 0x35, 0x36, 0x37] # Add all registers in the 0x8000 range for gfx6 if gfx_level == 'gfx6': @@ -667,6 +674,9 @@ enums_missing = { 'gfx9': { **missing_enums_gfx9, }, + 'gfx940': { + **missing_enums_gfx9, + }, 'gfx10': { **missing_enums_gfx81plus, "DB_DFSM_CONTROL__PUNCHOUT_MODE": DB_DFSM_CONTROL__PUNCHOUT_MODE, |