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authorAlyssa Rosenzweig <alyssa@rosenzweig.io>2023-05-15 10:18:18 -0400
committerMarge Bot <emma+marge@anholt.net>2023-05-16 22:36:21 +0000
commitc323762f9f3595ab272cdec955c4e435f975ded8 (patch)
tree30b2063f49275fa30bfd45a0078735a36dbe0169
parentec0c9706f0efb477559762daf55bd3ae0bfc3c52 (diff)
downloadmesa-c323762f9f3595ab272cdec955c4e435f975ded8.tar.gz
treewide: Stop lowering legacy atomics
There are no more producers of legacy atomics so these calls are inert. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by: Emma Anholt <emma@anholt.net> Reviewed-by: Jesse Natalie <jenatali@microsoft.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23036>
-rw-r--r--src/amd/vulkan/radv_shader.c4
-rw-r--r--src/asahi/compiler/agx_compile.c1
-rw-r--r--src/broadcom/compiler/vir.c3
-rw-r--r--src/broadcom/vulkan/v3dv_pipeline.c3
-rw-r--r--src/freedreno/ir3/ir3_nir.c3
-rw-r--r--src/freedreno/vulkan/tu_shader.cc3
-rw-r--r--src/gallium/auxiliary/gallivm/lp_bld_nir.c1
-rw-r--r--src/gallium/auxiliary/nir/nir_to_tgsi.c2
-rw-r--r--src/gallium/drivers/r600/sfn/sfn_nir.cpp1
-rw-r--r--src/gallium/drivers/radeonsi/si_shader_nir.c3
-rw-r--r--src/gallium/drivers/zink/zink_compiler.c3
-rw-r--r--src/gallium/frontends/lavapipe/lvp_pipeline.c1
-rw-r--r--src/intel/compiler/brw_nir.c2
-rw-r--r--src/microsoft/compiler/dxil_nir.c2
-rw-r--r--src/nouveau/codegen/nv50_ir_from_nir.cpp1
-rw-r--r--src/panfrost/compiler/bifrost_compile.c1
-rw-r--r--src/panfrost/midgard/midgard_compile.c2
-rw-r--r--src/panfrost/vulkan/panvk_vX_shader.c1
18 files changed, 1 insertions, 36 deletions
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index c692e50e9ab..7ca194eb46b 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -741,10 +741,6 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_pipeline_
radv_optimize_nir(nir, false);
}
- /* Temporary stopgap until legacy atomics are removed in the core */
- NIR_PASS_V(nir, nir_lower_legacy_atomics);
-
-
return nir;
}
diff --git a/src/asahi/compiler/agx_compile.c b/src/asahi/compiler/agx_compile.c
index 46887267339..90f94d8f06c 100644
--- a/src/asahi/compiler/agx_compile.c
+++ b/src/asahi/compiler/agx_compile.c
@@ -2380,7 +2380,6 @@ agx_preprocess_nir(nir_shader *nir, bool support_lod_bias)
NIR_PASS_V(nir, nir_opt_sink, move_all);
NIR_PASS_V(nir, nir_opt_move, move_all);
NIR_PASS_V(nir, agx_nir_lower_ubo);
- NIR_PASS_V(nir, nir_lower_legacy_atomics);
NIR_PASS_V(nir, agx_nir_lower_shared_bitsize);
}
diff --git a/src/broadcom/compiler/vir.c b/src/broadcom/compiler/vir.c
index 08ac97f6f48..5355645085d 100644
--- a/src/broadcom/compiler/vir.c
+++ b/src/broadcom/compiler/vir.c
@@ -617,9 +617,6 @@ type_size_vec4(const struct glsl_type *type, bool bindless)
static void
v3d_lower_nir(struct v3d_compile *c)
{
- /* FIXME: drop once GLSL/SPIR-V produce the new intrinsics. */
- NIR_PASS(_, c->s, nir_lower_legacy_atomics);
-
struct nir_lower_tex_options tex_options = {
.lower_txd = true,
.lower_tg4_broadcom_swizzle = true,
diff --git a/src/broadcom/vulkan/v3dv_pipeline.c b/src/broadcom/vulkan/v3dv_pipeline.c
index 3def20f37e5..e4eda5f6967 100644
--- a/src/broadcom/vulkan/v3dv_pipeline.c
+++ b/src/broadcom/vulkan/v3dv_pipeline.c
@@ -1708,9 +1708,6 @@ pipeline_lower_nir(struct v3dv_pipeline *pipeline,
assert(pipeline->shared_data &&
pipeline->shared_data->maps[p_stage->stage]);
- /* Temporary stopgap until legacy atomics are removed in core */
- NIR_PASS_V(p_stage->nir, nir_lower_legacy_atomics);
-
NIR_PASS_V(p_stage->nir, nir_vk_lower_ycbcr_tex,
lookup_ycbcr_conversion, layout);
diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c
index c0f40c7aa10..b1cf668421e 100644
--- a/src/freedreno/ir3/ir3_nir.c
+++ b/src/freedreno/ir3/ir3_nir.c
@@ -381,9 +381,6 @@ ir3_finalize_nir(struct ir3_compiler *compiler, nir_shader *s)
OPT_V(s, nir_remove_dead_variables, nir_var_function_temp, NULL);
- /* Temporary stopgap until the core is transitioned to unified atomics */
- OPT_V(s, nir_lower_legacy_atomics);
-
if (ir3_shader_debug & IR3_DBG_DISASM) {
mesa_logi("----------------------");
nir_log_shaderi(s);
diff --git a/src/freedreno/vulkan/tu_shader.cc b/src/freedreno/vulkan/tu_shader.cc
index a139df6ae05..39be10460db 100644
--- a/src/freedreno/vulkan/tu_shader.cc
+++ b/src/freedreno/vulkan/tu_shader.cc
@@ -1070,9 +1070,6 @@ tu_shader_create(struct tu_device *dev,
nir->info.stage == MESA_SHADER_GEOMETRY)
tu_gather_xfb_info(nir, &so_info);
- /* Temporary stopgap until legacy atomics are removed */
- NIR_PASS_V(nir, nir_lower_legacy_atomics);
-
NIR_PASS_V(nir, tu_lower_io, dev, shader, layout);
nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_nir.c b/src/gallium/auxiliary/gallivm/lp_bld_nir.c
index 75f2d44800b..34130b9d990 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_nir.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_nir.c
@@ -2668,7 +2668,6 @@ bool lp_build_nir_llvm(struct lp_build_nir_context *bld_base,
nir_lower_locals_to_regs(nir);
nir_remove_dead_derefs(nir);
nir_remove_dead_variables(nir, nir_var_function_temp, NULL);
- nir_lower_legacy_atomics(nir);
if (is_aos(bld_base)) {
nir_move_vec_src_uses_to_dest(nir);
diff --git a/src/gallium/auxiliary/nir/nir_to_tgsi.c b/src/gallium/auxiliary/nir/nir_to_tgsi.c
index cb95afa5383..1afa52d4ac9 100644
--- a/src/gallium/auxiliary/nir/nir_to_tgsi.c
+++ b/src/gallium/auxiliary/nir/nir_to_tgsi.c
@@ -3856,8 +3856,6 @@ const void *nir_to_tgsi_options(struct nir_shader *s,
source_mods |= nir_lower_fabs_source_mods;
NIR_PASS_V(s, nir_lower_to_source_mods, source_mods);
- NIR_PASS_V(s, nir_lower_legacy_atomics);
-
NIR_PASS_V(s, nir_convert_from_ssa, true);
NIR_PASS_V(s, nir_lower_vec_to_movs, ntt_vec_to_mov_writemask_cb, NULL);
diff --git a/src/gallium/drivers/r600/sfn/sfn_nir.cpp b/src/gallium/drivers/r600/sfn/sfn_nir.cpp
index 6d007fb2385..f35a62f1bf0 100644
--- a/src/gallium/drivers/r600/sfn/sfn_nir.cpp
+++ b/src/gallium/drivers/r600/sfn/sfn_nir.cpp
@@ -782,7 +782,6 @@ r600_finalize_nir(pipe_screen *screen, void *shader)
NIR_PASS_V(nir, r600_nir_lower_pack_unpack_2x16);
NIR_PASS_V(nir, r600_lower_shared_io);
- NIR_PASS_V(nir, nir_lower_legacy_atomics);
NIR_PASS_V(nir, r600_nir_lower_atomics);
if (rs->b.gfx_level == CAYMAN)
diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c b/src/gallium/drivers/radeonsi/si_shader_nir.c
index a75c393d19d..7ffd9ef57e3 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -375,9 +375,6 @@ static void si_lower_nir(struct si_screen *sscreen, struct nir_shader *nir)
si_late_optimize_16bit_samplers(sscreen, nir);
NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_function_temp, NULL);
-
- /* Temporary stopgap until legacy atomics are removed in the core */
- NIR_PASS_V(nir, nir_lower_legacy_atomics);
}
static bool si_mark_divergent_texture_non_uniform(struct nir_shader *nir)
diff --git a/src/gallium/drivers/zink/zink_compiler.c b/src/gallium/drivers/zink/zink_compiler.c
index 34203bb45dd..21bdee34965 100644
--- a/src/gallium/drivers/zink/zink_compiler.c
+++ b/src/gallium/drivers/zink/zink_compiler.c
@@ -4874,9 +4874,6 @@ zink_shader_create(struct zink_screen *screen, struct nir_shader *nir,
NIR_PASS_V(nir, nir_lower_fragcolor,
nir->info.fs.color_is_dual_source ? 1 : 8);
- /* Temporary stop gap until glsl-to-nir produces unified atomics */
- NIR_PASS_V(nir, nir_lower_legacy_atomics);
-
NIR_PASS_V(nir, lower_64bit_vertex_attribs);
bool needs_size = analyze_io(ret, nir);
NIR_PASS_V(nir, unbreak_bos, ret, needs_size);
diff --git a/src/gallium/frontends/lavapipe/lvp_pipeline.c b/src/gallium/frontends/lavapipe/lvp_pipeline.c
index 95e301663c8..3be265f0f40 100644
--- a/src/gallium/frontends/lavapipe/lvp_pipeline.c
+++ b/src/gallium/frontends/lavapipe/lvp_pipeline.c
@@ -464,7 +464,6 @@ lvp_shader_lower(struct lvp_device *pdevice, nir_shader *nir, struct lvp_shader
NIR_PASS_V(nir, nir_remove_dead_variables,
nir_var_uniform | nir_var_image, NULL);
- NIR_PASS_V(nir, nir_lower_legacy_atomics);
scan_pipeline_info(shader, layout, nir);
optimize(nir);
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index a507c62a5d4..ff49205a8ed 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -932,8 +932,6 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir,
OPT(nir_lower_frexp);
- OPT(nir_lower_legacy_atomics);
-
if (is_scalar) {
OPT(nir_lower_alu_to_scalar, NULL, NULL);
}
diff --git a/src/microsoft/compiler/dxil_nir.c b/src/microsoft/compiler/dxil_nir.c
index 5961b31131b..46db17b9734 100644
--- a/src/microsoft/compiler/dxil_nir.c
+++ b/src/microsoft/compiler/dxil_nir.c
@@ -790,7 +790,7 @@ lower_shared_atomic(nir_builder *b, nir_intrinsic_instr *intr)
bool
dxil_nir_lower_atomics_to_dxil(nir_shader *nir)
{
- bool progress = nir_lower_legacy_atomics(nir);
+ bool progress = false;
foreach_list_typed(nir_function, func, node, &nir->functions) {
if (!func->is_entrypoint)
diff --git a/src/nouveau/codegen/nv50_ir_from_nir.cpp b/src/nouveau/codegen/nv50_ir_from_nir.cpp
index 3ab457a651c..3652ef440d7 100644
--- a/src/nouveau/codegen/nv50_ir_from_nir.cpp
+++ b/src/nouveau/codegen/nv50_ir_from_nir.cpp
@@ -3206,7 +3206,6 @@ Converter::run()
type_size, (nir_lower_io_options)0);
NIR_PASS_V(nir, nir_lower_subgroups, &subgroup_options);
- NIR_PASS_V(nir, nir_lower_legacy_atomics);
struct nir_lower_tex_options tex_options = {};
tex_options.lower_txp = ~0;
diff --git a/src/panfrost/compiler/bifrost_compile.c b/src/panfrost/compiler/bifrost_compile.c
index 44d8f87e44c..fc36cd2dae6 100644
--- a/src/panfrost/compiler/bifrost_compile.c
+++ b/src/panfrost/compiler/bifrost_compile.c
@@ -4436,7 +4436,6 @@ bi_optimize_nir(nir_shader *nir, unsigned gpu_id, bool is_blend)
NIR_PASS(progress, nir, nir_opt_cse);
}
- NIR_PASS(progress, nir, nir_lower_legacy_atomics);
NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
NIR_PASS(progress, nir, nir_opt_dce);
diff --git a/src/panfrost/midgard/midgard_compile.c b/src/panfrost/midgard/midgard_compile.c
index 80795a1de98..e80d491d570 100644
--- a/src/panfrost/midgard/midgard_compile.c
+++ b/src/panfrost/midgard/midgard_compile.c
@@ -395,8 +395,6 @@ midgard_preprocess_nir(nir_shader *nir, unsigned gpu_id)
if (quirks & MIDGARD_BROKEN_LOD)
NIR_PASS_V(nir, midgard_nir_lod_errata);
- NIR_PASS_V(nir, nir_lower_legacy_atomics);
-
/* Midgard image ops coordinates are 16-bit instead of 32-bit */
NIR_PASS_V(nir, midgard_nir_lower_image_bitsize);
diff --git a/src/panfrost/vulkan/panvk_vX_shader.c b/src/panfrost/vulkan/panvk_vX_shader.c
index 06c68d18837..483a44e5a43 100644
--- a/src/panfrost/vulkan/panvk_vX_shader.c
+++ b/src/panfrost/vulkan/panvk_vX_shader.c
@@ -314,7 +314,6 @@ panvk_per_arch(shader_create)(struct panvk_device *dev, gl_shader_stage stage,
.lower_invalid_implicit_lod = true,
};
NIR_PASS_V(nir, nir_lower_tex, &lower_tex_options);
- NIR_PASS_V(nir, nir_lower_legacy_atomics);
NIR_PASS_V(nir, panvk_per_arch(nir_lower_descriptors), dev, layout,
&shader->has_img_access);