summaryrefslogtreecommitdiff
path: root/gcc/config/aarch64/aarch64-simd.md
Commit message (Expand)AuthorAgeFilesLines
* [AArch64] Fix some reg-to-reg move scheduler types.ktkachov2014-06-101-1/+1
* [AArch64] Add a big-endian lane flip at expand-time in saturating math patterns.ktkachov2014-06-101-5/+117
* * config/aarch64/aarch64.c (aarch64_classify_address)amker2014-06-041-8/+8
* Recognize shuffle patterns for REV instructions on AArch64, rewrite intrinsics.alalaw012014-06-031-0/+9
* Detect EXT patterns to vec_perm_const, use for EXT intrinsicsalalaw012014-05-291-0/+29
* [AArch64] Improve vst4_lane intrinsicsjgreenhalgh2014-04-281-0/+84
* [AArch64] Vectorise bswap[16,32,64]ktkachov2014-04-241-0/+8
* [AArch64] 64-bit float vreinterpret implementionmshawcroft2014-04-221-0/+9
* [AArch64] vqneg and vqabs intrinsics implementation.mshawcroft2014-04-221-3/+3
* Re: [AArch64] Fix possible wrong code generation when comparing DImode values.jgreenhalgh2014-04-221-45/+105
* [AArch64] vrnd<*>_f64 patchmshawcroft2014-04-221-1/+1
* [ARM/AArch64][1/2] Crypto intrinsics tuning for Cortex-A53 - "type" Attribute...ktkachov2014-03-281-2/+2
* [AArch64] Logical vector shift right conformancejgreenhalgh2014-03-241-0/+25
* [AArch64] Shift right pattern fixjgreenhalgh2014-02-061-1/+1
* [PATCH][AArch64] Vector shift by 64 fixjgreenhalgh2014-01-231-0/+26
* [AArch64_BE 3/4] Big-Endian lane numbering fixktkachov2014-01-231-21/+96
* [AArch64_BE 2/4] Big-Endian lane numbering fixktkachov2014-01-231-0/+14
* [AArch64_BE 1/4] Big-Endian lane numbering fixktkachov2014-01-231-2/+28
* [AArch64] Disable vec_perm patterns for aarch64_be.mshawcroft2014-01-201-1/+1
* Update copyright years in gcc/rsandifo2014-01-021-1/+1
* Implement support for AArch64 Crypto PMULL.64.belagod2013-12-191-0/+22
* Implement support for AArch64 Crypto SHA256.belagod2013-12-191-0/+34
* Implement support for AArch64 Crypto SHA1.belagod2013-12-191-0/+43
* Implement support for AArch64 Crypto AES.belagod2013-12-191-0/+22
* [AArch64] [3/4 Fix vtbx1]Implement bsl intrinsics using builtinsjgreenhalgh2013-11-261-9/+9
* 2013-11-22 Tejas Belagod <tejas.belagod@arm.com>belagod2013-11-221-28/+9
* 2013-11-22 Tejas Belagod <tejas.belagod@arm.com>belagod2013-11-221-7/+20
* 2013-11-22 Tejas Belagod <tejas.belagod@arm.com>belagod2013-11-221-28/+67
* 2013-11-22 Tejas Belagod <tejas.belagod@arm.com>belagod2013-11-221-8/+8
* [AArch64] Remove simd_typejgreenhalgh2013-11-151-759/+202
* 2013-11-13 Tejas Belagod <tejas.belagod@arm.com>belagod2013-11-131-0/+16
* 2013-11-13 Tejas Belagod <tejas.belagod@arm.com>belagod2013-11-131-20/+24
* [AArch64] [Neon types 4/10] Add type attributes to all simd insnsjgreenhalgh2013-10-151-78/+193
* gcc/vp2013-10-011-8/+23
* [AArch64] Improve arm_neon.h vml<as>_lane handling.jgreenhalgh2013-09-161-0/+195
* [AArch64] Implement vmul<q>_lane<q>_<fsu><16,32,64> intrinsics in Cjgreenhalgh2013-09-161-0/+53
* [AArch64, ARM] Rename the FCPYS type to FMOVjgreenhalgh2013-09-061-1/+1
* [Patch AArch64] Fix register constraints for lane intrinsics.jgreenhalgh2013-09-061-4/+4
* [AArch64] Fix categorisation of the frecp* insns.jgreenhalgh2013-09-051-4/+14
* [AArch64] Rewrite the vdup_lane intrinsics in Cjgreenhalgh2013-09-021-12/+27
* [AArch64] Fixup the vget_lane RTL patterns and intrinsicsjgreenhalgh2013-08-091-33/+24
* * config/aarch64/aarch64.md (define_attr "type"): Delete.sofiane2013-08-011-0/+1
* [AArch64] Convert ld1, st1 arm_neon.h intrinsics to RTL builtins.jgreenhalgh2013-07-031-0/+22
* gcc/sofiane2013-06-171-19/+8
* gcc/ChangeLogvp2013-06-141-0/+98
* * config/aarch64/aarch64-simd.md (aarch64_combine<mode>): convert to split.sofiane2013-06-121-5/+19
* Ok, I've removed what you previously asked me to include!sofiane2013-06-111-3/+3
* AArch64 - Improve MOVI handling (4/5)ibolton2013-06-041-2/+2
* [AArch64] Support for CLZmshawcroft2013-05-231-0/+9
* [AArch64] Fix possible wrong code generation when comparing DImode values.jgreenhalgh2013-05-231-32/+10
View Lorry Controller Status