diff options
| author | jgreenhalgh <jgreenhalgh@138bc75d-0d04-0410-961f-82ee72b054a4> | 2014-03-24 12:05:38 +0000 |
|---|---|---|
| committer | jgreenhalgh <jgreenhalgh@138bc75d-0d04-0410-961f-82ee72b054a4> | 2014-03-24 12:05:38 +0000 |
| commit | bed34e8314ab4f7439bcda61eb221ae13833200d (patch) | |
| tree | 0536898809d3385d86f90859795ab748be327a4f /gcc/config/aarch64/aarch64-simd.md | |
| parent | d040c0373b530e352f4f644a9ce46ea8dabfe7e1 (diff) | |
| download | gcc-bed34e8314ab4f7439bcda61eb221ae13833200d.tar.gz | |
[AArch64] Logical vector shift right conformance
gcc/
* config/aarch64/aarch64-simd-builtins.def (lshr): DI mode excluded.
(lshr_simd): DI mode added.
* config/aarch64/aarch64-simd.md (aarch64_lshr_simddi): New pattern.
(aarch64_ushr_simddi): Likewise.
* config/aarch64/aarch64.md (UNSPEC_USHR64): New unspec.
* config/aarch64/arm_neon.h (vshr_n_u64): Intrinsic fixed.
(vshrd_n_u64): Likewise.
gcc/testsuite/
* gcc.target/aarch64/ushr64_1.c: New testcase.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208789 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/aarch64/aarch64-simd.md')
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 4dffb59e856..6048d605c72 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -724,6 +724,31 @@ DONE; }) +(define_expand "aarch64_lshr_simddi" + [(match_operand:DI 0 "register_operand" "=w") + (match_operand:DI 1 "register_operand" "w") + (match_operand:SI 2 "aarch64_shift_imm64_di" "")] + "TARGET_SIMD" + { + if (INTVAL (operands[2]) == 64) + emit_insn (gen_aarch64_ushr_simddi (operands[0], operands[1])); + else + emit_insn (gen_lshrdi3 (operands[0], operands[1], operands[2])); + DONE; + } +) + +;; SIMD shift by 64. This pattern is a special case as standard pattern does +;; not handle NEON shifts by 64. +(define_insn "aarch64_ushr_simddi" + [(set (match_operand:DI 0 "register_operand" "=w") + (unspec:DI + [(match_operand:DI 1 "register_operand" "w")] UNSPEC_USHR64))] + "TARGET_SIMD" + "ushr\t%d0, %d1, 64" + [(set_attr "type" "neon_shift_imm")] +) + (define_expand "vec_set<mode>" [(match_operand:VQ_S 0 "register_operand") (match_operand:<VEL> 1 "register_operand") |