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| author | jgreenhalgh <jgreenhalgh@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-09-16 09:50:21 +0000 |
|---|---|---|
| committer | jgreenhalgh <jgreenhalgh@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-09-16 09:50:21 +0000 |
| commit | 5839dcd41ae3384fa4ae42c4f4f58443c645ce40 (patch) | |
| tree | 4d1dcfabd30aa74d7ff264150aab3706bc9769e6 /gcc/config/aarch64/aarch64-simd.md | |
| parent | d7438495094175f4aa5233bbce38308d4eb40b34 (diff) | |
| download | gcc-5839dcd41ae3384fa4ae42c4f4f58443c645ce40.tar.gz | |
[AArch64] Implement vmul<q>_lane<q>_<fsu><16,32,64> intrinsics in C
gcc/
* config/aarch64/aarch64-simd.md (aarch64_mul3_elt<mode>): New.
(aarch64_mul3_elt_<vswap_width_name><mode>): Likewise.
(aarch64_mul3_elt_to_128df): Likewise.
(aarch64_mul3_elt_to_64v2df): Likewise.
* config/aarch64/iterators.md (VEL): Also handle DFmode.
(VMUL): New.
(VMUL_CHANGE_NLANES) Likewise.
(h_con): Likewise.
(f): Likewise.
* config/aarch64/arm_neon.h
(vmul<q>_lane<q>_<suf><16,32,64>): Convert to C implementation.
gcc/testsuite/
* gcc.target/aarch64/mul_intrinsic_1.c: New.
* gcc.target/aarch64/fmul_intrinsic_1.c: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@202624 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/aarch64/aarch64-simd.md')
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 9805197a22b..04d5794ffca 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -582,6 +582,59 @@ (set_attr "simd_mode" "<MODE>")] ) +(define_insn "*aarch64_mul3_elt<mode>" + [(set (match_operand:VMUL 0 "register_operand" "=w") + (mult:VMUL + (vec_duplicate:VMUL + (vec_select:<VEL> + (match_operand:VMUL 1 "register_operand" "<h_con>") + (parallel [(match_operand:SI 2 "immediate_operand")]))) + (match_operand:VMUL 3 "register_operand" "w")))] + "TARGET_SIMD" + "<f>mul\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]" + [(set_attr "simd_type" "simd_<f>mul_elt") + (set_attr "simd_mode" "<MODE>")] +) + +(define_insn "*aarch64_mul3_elt_<vswap_width_name><mode>" + [(set (match_operand:VMUL_CHANGE_NLANES 0 "register_operand" "=w") + (mult:VMUL_CHANGE_NLANES + (vec_duplicate:VMUL_CHANGE_NLANES + (vec_select:<VEL> + (match_operand:<VSWAP_WIDTH> 1 "register_operand" "<h_con>") + (parallel [(match_operand:SI 2 "immediate_operand")]))) + (match_operand:VMUL_CHANGE_NLANES 3 "register_operand" "w")))] + "TARGET_SIMD" + "<f>mul\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]" + [(set_attr "simd_type" "simd_<f>mul_elt") + (set_attr "simd_mode" "<MODE>")] +) + +(define_insn "*aarch64_mul3_elt_to_128df" + [(set (match_operand:V2DF 0 "register_operand" "=w") + (mult:V2DF + (vec_duplicate:V2DF + (match_operand:DF 2 "register_operand" "w")) + (match_operand:V2DF 1 "register_operand" "w")))] + "TARGET_SIMD" + "fmul\\t%0.2d, %1.2d, %2.d[0]" + [(set_attr "simd_type" "simd_fmul_elt") + (set_attr "simd_mode" "V2DF")] +) + +(define_insn "*aarch64_mul3_elt_to_64v2df" + [(set (match_operand:DF 0 "register_operand" "=w") + (mult:DF + (vec_select:DF + (match_operand:V2DF 1 "register_operand" "w") + (parallel [(match_operand:SI 2 "immediate_operand")])) + (match_operand:DF 3 "register_operand" "w")))] + "TARGET_SIMD" + "fmul\\t%0.2d, %3.2d, %1.d[%2]" + [(set_attr "simd_type" "simd_fmul_elt") + (set_attr "simd_mode" "V2DF")] +) + (define_insn "neg<mode>2" [(set (match_operand:VDQ 0 "register_operand" "=w") (neg:VDQ (match_operand:VDQ 1 "register_operand" "w")))] |