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* Update ARM feature detection macrosJeffrey Walton2021-03-071-28/+30
| | | | Cross your fingers... This is an absolute mess...
* Update documentationsJeffrey Walton2021-03-051-4/+4
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* Update cpu.cpp features for Apple M1Jeffrey Walton2021-03-051-12/+12
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* Whitespace check-inJeffrey Walton2021-03-041-1/+1
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* Fix typos in documentation and comments (PR #1012)Tobias Nießen2021-03-041-1/+1
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* Use \return and \throw consitently in the docsJeffrey Walton2020-12-071-42/+42
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* Whitespace check-inJeffrey Walton2020-02-101-2/+2
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* Add external reference to g_hasMOVBEJeffrey Walton2020-02-101-0/+1
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* Add HasMOVBE() on Intel machinesJeffrey Walton2020-02-101-19/+36
| | | | Also update documentation
* Whitespace check-inJeffrey Walton2020-02-101-77/+77
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* Set g_x86DetectionDone when CRYPTOPP_DISABLE_ASM is in effectJeffrey Walton2020-01-231-3/+1
| | | | Previously we were re-entering DetectX86Features when CpuId failed or CRYPTOPP_DISABLE_ASM was in effect
* Fix AIX and Linux compiles for PowerPC (PR #902)Jeffrey Walton2019-10-231-3/+38
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* Fix Rijndael recursion overflow when -DCRYPTOPP_DISABLE_SSSE3 (GH #880, PR #886)Jeffrey Walton2019-09-281-13/+79
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* Prepare for Crypto++ 8.0 releaseJeffrey Walton2018-12-271-7/+7
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* Update comments in config.hJeffrey Walton2018-12-091-2/+2
| | | | | Some comments in config.h were old. Time for a refresh. Switch from CRYPTOPP_BOOL_ARM64 to CRYPTOPP_BOOL_ARMV8. Aarch32 is ARMv8, and that's the important part.
* Add CRYPTOPP_DISABLE_MIXED_ASM define and feature test (GH #756, PR #757)Jeffrey Walton2018-12-051-1/+1
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* Update documentationJeffrey Walton2018-11-301-15/+6
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* Update documentationJeffrey Walton2018-11-301-5/+1
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* Add Power9 Random Number Generator support (GH #747, PR #748)Jeffrey Walton2018-11-271-7/+43
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* Rename files with dashes to underscores (GH #736)Jeffrey Walton2018-11-101-2/+2
| | | | Also see https://groups.google.com/forum/#!topic/cryptopp-users/HBz-6gZZFOA on the mailing list
* Prepare for POWER8 carryless multiplies using vpmsumJeffrey Walton2018-08-061-13/+43
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* Add ARMv8 CPU feature queries (GH #685)Jeffrey Walton2018-07-141-16/+105
| | | | CPU feature probes are still outstanding. They are going to be trickier because if CRYPTOPP_XXX_FEATURE_AVAILABLE
* Add ARMv7 cpu detectionJeffrey Walton2018-07-081-1/+17
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* Add AVX and AVX2 runtime feature detection (GH #671)Jeffrey Walton2018-06-181-0/+30
| | | | There are no corresponding defines in config.h at the moment. Programs will have to use the preprocessor macros __AVX__ and __AVX2__ to determine when they are available.
* Workaround for #636alanbirtles2018-04-121-0/+5
| | | Temporarily switch to AT&T syntax in ASJ for clang 5.0.0+ and apple clang 9.0.0+ to workaround https://bugs.llvm.org/show_bug.cgi?id=36144
* Change Doxygen comment style from //! to ///Jeffrey Walton2017-11-291-213/+213
| | | | Also see https://groups.google.com/forum/#!topic/cryptopp-users/A7-Xt5Knlzw
* Add sse-simd.cpp to nmake file and vcxproj filtersJeffrey Walton2017-11-161-2/+2
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* Update documentationJeffrey Walton2017-11-161-2/+24
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* Fix SunCC 12.2 compiler crash with GCM_Xor16_SSE2Jeffrey Walton2017-11-161-0/+12
| | | | SunCC 12.3 through 12.5 still cannot handle CLMUL, though. It would be nice if Sun fixed the regression.
* Update documentationJeffrey Walton2017-11-121-0/+16
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* Cleanup Altivec and Power7 code pathsJeffrey Walton2017-10-171-2/+25
| | | | This changes the dependency from Altivec to Power7. Internally we needed Power7 but it was cut-in as a pseudo Altivec dependency. Also see http://groups.google.com/forum/#!topic/cryptopp-users/fmEKOG41SG8
* Add Power8 SHA256 and SHA512 support (GH #513)Jeffrey Walton2017-09-221-9/+9
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* Update documentationJeffrey Walton2017-09-111-18/+24
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* Add PowerPC support to cpu.h and validate.cppJeffrey Walton2017-09-111-1/+107
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* Fix IS_ARMV8 in GNUmakefileJeffrey Walton2017-08-301-0/+4
| | | | Fix guard for HasPMULL()
* Remove BOOL macro value (GH #462)Jeffrey Walton2017-08-201-1/+1
| | | | Currently the CRYPTOPP_BOOL_XXX macros set the macro value to 0 or 1. If we remove setting the 0 value (the #else part of the expression), then the self tests speed up by about 0.3 seconds. I can't explain it, but I have observed it repeatedly. This check-in prepares for the removal in Upstream master
* Update documentationJeffrey Walton2017-08-171-0/+4
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* Update documentationJeffrey Walton2017-08-171-14/+33
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* Split source files to support Base Implementation + SIMD implementation (GH ↵Jeffrey Walton2017-08-171-121/+50
| | | | | #461) Split source files to support Base Implementation + SIMD implementation
* Fix NEON detection on Aarch32 and Aarch64Jeffrey Walton2017-08-171-1/+1
| | | | I wish GCC would get its head out of its ass and define the apprpriate defines. NEON/ASIMD cannot be disgorged from Aarch32/Aarch64 just like SSE2 cannot be disgorged from x86_64. They are core instruction sets
* Add defines for GCC_INLINE and GCC_INLINE_ATTRIB (Issues 427 and 428)Jeffrey Walton2017-05-201-0/+12
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* Fix SunCC and "_mm_set_epi8 must have prototype"Jeffrey Walton2017-04-221-1/+1
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* Fix ARM compile under VS2013Jeffrey Walton2017-03-201-1/+1
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* Change file preamble to include "originally written by Wei Dai"Jeffrey Walton2017-01-271-1/+1
| | | | We have made a fair number of changes, and we don't want WD to receive credit for issues he was not part of
* VEXT_8 -> VEXT_U8Jeffrey Walton2017-01-221-1/+1
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* Begin fix of cpu.h under Apple and LLVM Clang (Issue 362)Jeffrey Walton2017-01-131-1/+1
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* Add ARM SHA extensions for SHA1Jeffrey Walton2017-01-131-4/+7
| | | | Benchmarking on ARMv8/Aarch64 dev-board shows SHA-1 speeds up by 2.5x
* spelling fixesklemens2016-12-271-1/+1
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* Silence select conversion warnings (Issue 340)Jeffrey Walton2016-12-021-0/+12
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* Add Intel SHA1 extension supportJeffrey Walton2016-12-011-6/+3
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