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author | Jeffrey Walton <noloader@gmail.com> | 2017-11-12 16:35:44 -0500 |
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committer | Jeffrey Walton <noloader@gmail.com> | 2017-11-12 16:35:44 -0500 |
commit | b40ca9755094a33f9d438aee3b2cc476cfc04e07 (patch) | |
tree | 277ef485db2d5310e12feb3ebe32ec8c9bcb83aa /cpu.h | |
parent | 81f0b9bd83ed2b4b98b0f3d49e2b71fba90aae3f (diff) | |
download | cryptopp-git-b40ca9755094a33f9d438aee3b2cc476cfc04e07.tar.gz |
Update documentation
Diffstat (limited to 'cpu.h')
-rw-r--r-- | cpu.h | 16 |
1 files changed, 16 insertions, 0 deletions
@@ -80,6 +80,9 @@ CRYPTOPP_DLL void CRYPTOPP_API DetectX86Features(); CRYPTOPP_DLL bool CRYPTOPP_API CpuId(word32 func, word32 subfunc, word32 output[4]);
#endif // CRYPTOPP_DOXYGEN_PROCESSING
+//! \name IA-32 CPU FEATURES
+//@{
+
//! \brief Determines SSE2 availability
//! \returns true if SSE2 is determined to be available, false otherwise
//! \details MMX, SSE and SSE2 are core processor features for x86_64, and
@@ -264,6 +267,8 @@ inline int GetCacheLineSize() DetectX86Features();
return g_cacheLineSize;
}
+//@}
+
#endif // CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64
// ***************************** ARM-32, Aarch32 and Aarch64 ***************************** //
@@ -277,6 +282,9 @@ extern bool g_hasNEON, g_hasPMULL, g_hasCRC32, g_hasAES, g_hasSHA1, g_hasSHA2; void CRYPTOPP_API DetectArmFeatures();
#endif // CRYPTOPP_DOXYGEN_PROCESSING
+//! \name ARM A-32, Aarch32 and AArch64 CPU FEATURES
+//@{
+
//! \brief Determine if an ARM processor has Advanced SIMD available
//! \returns true if the hardware is capable of Advanced SIMD at runtime, false otherwise.
//! \details Advanced SIMD instructions are available under most ARMv7, Aarch32 and Aarch64.
@@ -389,6 +397,9 @@ inline bool HasSHA2() return false;
#endif
}
+
+//@}
+
#endif // CRYPTOPP_BOOL_ARM32 || CRYPTOPP_BOOL_ARM64
// ***************************** PowerPC ***************************** //
@@ -403,6 +414,9 @@ extern word32 g_cacheLineSize; void CRYPTOPP_API DetectPowerpcFeatures();
#endif // CRYPTOPP_DOXYGEN_PROCESSING
+//! \name POWERPC CPU FEATURES
+//@{
+
//! \brief Determine if a PowerPC processor has Altivec available
//! \returns true if the hardware is capable of Altivec at runtime, false otherwise.
//! \details Altivec instructions are available under most modern PowerPCs.
@@ -511,6 +525,8 @@ inline int GetCacheLineSize() return g_cacheLineSize;
}
+//@}
+
#endif // CRYPTOPP_BOOL_PPC32 || CRYPTOPP_BOOL_PPC64
// ***************************** L1 cache line ***************************** //
|