Change Doxygen comment style from //! to ///

Also see https://groups.google.com/forum/#!topic/cryptopp-users/A7-Xt5Knlzw

1 files changed, 213 insertions, 213 deletions

diff --git a/cpu.h b/cpu.h
index 481d578d..fa0158be 100644
--- a/cpu.h
+++ b/cpu.h
@@ -2,30 +2,30 @@
 //         updated for ARM and PowerPC by Jeffrey Walton.

 //         updated to split CPU_Query() and CPU_Probe() by Jeffrey Walton.

 

-//! \file cpu.h

-//! \brief Functions for CPU features and intrinsics

-//! \details The CPU functions are used in IA-32, ARM and PowerPC code paths. The

-//!   functions provide cpu specific feature testing on IA-32, ARM and PowerPC machines.

-//! \details Feature detection uses CPUID on IA-32, like Intel and AMD. On other platforms

-//!   a two-part strategy is used. First, the library attempts to *Query* the OS for a feature,

-//!   like using Linux getauxval() or android_getCpuFeatures(). If that fails, then *Probe*

-//!   the cpu executing an instruction and an observe a SIGILL if unsupported. The general

-//!   pattern used by the library is:

-//! <pre>

-//!     g_hasCRC32 = CPU_QueryCRC32() || CPU_ProbeCRC32();

-//!     g_hasPMULL = CPU_QueryPMULL() || CPU_ProbePMULL();

-//!     g_hasAES  = CPU_QueryAES() || CPU_ProbeAES();

-//! </pre>

-//! \details Generally speaking, CPU_Query() is in the source file <tt>cpu.cpp</tt> because it

-//!   does not require special architectural flags. CPU_Probe() is in a source file that recieves

-//!   architectural flags, like <tt>sse-simd.cpp</tt>, <tt>neon-simd.cpp</tt> and

-//!   <tt>ppc-simd.cpp</tt>. For example, compiling <tt>neon-simd.cpp</tt> on an ARM64 machine will

-//!   have <tt>-march=armv8-a</tt> applied during a compile to make the instruction set architecture

-//!   (ISA) available.

-//! \details The cpu probes are expensive when compared to a standard OS feature query. The library

-//!   also avoids probes on Apple platforms because Apple's signal handling for SIGILLs appears to

-//!   corrupt memory. CPU_Probe() will unconditionally return false for Apple platforms. OpenSSL

-//!   experienced the same problem and moved away from SIGILL probes on Apple.

+/// \file cpu.h

+/// \brief Functions for CPU features and intrinsics

+/// \details The CPU functions are used in IA-32, ARM and PowerPC code paths. The

+///   functions provide cpu specific feature testing on IA-32, ARM and PowerPC machines.

+/// \details Feature detection uses CPUID on IA-32, like Intel and AMD. On other platforms

+///   a two-part strategy is used. First, the library attempts to *Query* the OS for a feature,

+///   like using Linux getauxval() or android_getCpuFeatures(). If that fails, then *Probe*

+///   the cpu executing an instruction and an observe a SIGILL if unsupported. The general

+///   pattern used by the library is:

+/// <pre>

+///     g_hasCRC32 = CPU_QueryCRC32() || CPU_ProbeCRC32();

+///     g_hasPMULL = CPU_QueryPMULL() || CPU_ProbePMULL();

+///     g_hasAES  = CPU_QueryAES() || CPU_ProbeAES();

+/// </pre>

+/// \details Generally speaking, CPU_Query() is in the source file <tt>cpu.cpp</tt> because it

+///   does not require special architectural flags. CPU_Probe() is in a source file that recieves

+///   architectural flags, like <tt>sse-simd.cpp</tt>, <tt>neon-simd.cpp</tt> and

+///   <tt>ppc-simd.cpp</tt>. For example, compiling <tt>neon-simd.cpp</tt> on an ARM64 machine will

+///   have <tt>-march=armv8-a</tt> applied during a compile to make the instruction set architecture

+///   (ISA) available.

+/// \details The cpu probes are expensive when compared to a standard OS feature query. The library

+///   also avoids probes on Apple platforms because Apple's signal handling for SIGILLs appears to

+///   corrupt memory. CPU_Probe() will unconditionally return false for Apple platforms. OpenSSL

+///   experienced the same problem and moved away from SIGILL probes on Apple.

 

 #ifndef CRYPTOPP_CPU_H

 #define CRYPTOPP_CPU_H

@@ -103,14 +103,14 @@ CRYPTOPP_DLL void CRYPTOPP_API DetectX86Features();
 CRYPTOPP_DLL bool CRYPTOPP_API CpuId(word32 func, word32 subfunc, word32 output[4]);

 #endif // CRYPTOPP_DOXYGEN_PROCESSING

 

-//! \name IA-32 CPU FEATURES

+/// \name IA-32 CPU FEATURES

 //@{

 

-//! \brief Determines SSE2 availability

-//! \returns true if SSE2 is determined to be available, false otherwise

-//! \details MMX, SSE and SSE2 are core processor features for x86_64, and

-//!   the function always returns true for the platform.

-//! \note This function is only available on Intel IA-32 platforms

+/// \brief Determines SSE2 availability

+/// \returns true if SSE2 is determined to be available, false otherwise

+/// \details MMX, SSE and SSE2 are core processor features for x86_64, and

+///   the function always returns true for the platform.

+/// \note This function is only available on Intel IA-32 platforms

 inline bool HasSSE2()

 {

 #if CRYPTOPP_BOOL_X64

@@ -122,10 +122,10 @@ inline bool HasSSE2()
 #endif

 }

 

-//! \brief Determines SSSE3 availability

-//! \returns true if SSSE3 is determined to be available, false otherwise

-//! \details HasSSSE3() is a runtime check performed using CPUID

-//! \note This function is only available on Intel IA-32 platforms

+/// \brief Determines SSSE3 availability

+/// \returns true if SSSE3 is determined to be available, false otherwise

+/// \details HasSSSE3() is a runtime check performed using CPUID

+/// \note This function is only available on Intel IA-32 platforms

 inline bool HasSSSE3()

 {

 	if (!g_x86DetectionDone)

@@ -133,10 +133,10 @@ inline bool HasSSSE3()
 	return g_hasSSSE3;

 }

 

-//! \brief Determines SSE4.1 availability

-//! \returns true if SSE4.1 is determined to be available, false otherwise

-//! \details HasSSE41() is a runtime check performed using CPUID

-//! \note This function is only available on Intel IA-32 platforms

+/// \brief Determines SSE4.1 availability

+/// \returns true if SSE4.1 is determined to be available, false otherwise

+/// \details HasSSE41() is a runtime check performed using CPUID

+/// \note This function is only available on Intel IA-32 platforms

 inline bool HasSSE41()

 {

 	if (!g_x86DetectionDone)

@@ -144,10 +144,10 @@ inline bool HasSSE41()
 	return g_hasSSE41;

 }

 

-//! \brief Determines SSE4.2 availability

-//! \returns true if SSE4.2 is determined to be available, false otherwise

-//! \details HasSSE42() is a runtime check performed using CPUID

-//! \note This function is only available on Intel IA-32 platforms

+/// \brief Determines SSE4.2 availability

+/// \returns true if SSE4.2 is determined to be available, false otherwise

+/// \details HasSSE42() is a runtime check performed using CPUID

+/// \note This function is only available on Intel IA-32 platforms

 inline bool HasSSE42()

 {

 	if (!g_x86DetectionDone)

@@ -155,10 +155,10 @@ inline bool HasSSE42()
 	return g_hasSSE42;

 }

 

-//! \brief Determines AES-NI availability

-//! \returns true if AES-NI is determined to be available, false otherwise

-//! \details HasAESNI() is a runtime check performed using CPUID

-//! \note This function is only available on Intel IA-32 platforms

+/// \brief Determines AES-NI availability

+/// \returns true if AES-NI is determined to be available, false otherwise

+/// \details HasAESNI() is a runtime check performed using CPUID

+/// \note This function is only available on Intel IA-32 platforms

 inline bool HasAESNI()

 {

 	if (!g_x86DetectionDone)

@@ -166,10 +166,10 @@ inline bool HasAESNI()
 	return g_hasAESNI;

 }

 

-//! \brief Determines Carryless Multiply availability

-//! \returns true if pclmulqdq is determined to be available, false otherwise

-//! \details HasCLMUL() is a runtime check performed using CPUID

-//! \note This function is only available on Intel IA-32 platforms

+/// \brief Determines Carryless Multiply availability

+/// \returns true if pclmulqdq is determined to be available, false otherwise

+/// \details HasCLMUL() is a runtime check performed using CPUID

+/// \note This function is only available on Intel IA-32 platforms

 inline bool HasCLMUL()

 {

 	if (!g_x86DetectionDone)

@@ -177,10 +177,10 @@ inline bool HasCLMUL()
 	return g_hasCLMUL;

 }

 

-//! \brief Determines SHA availability

-//! \returns true if SHA is determined to be available, false otherwise

-//! \details HasSHA() is a runtime check performed using CPUID

-//! \note This function is only available on Intel IA-32 platforms

+/// \brief Determines SHA availability

+/// \returns true if SHA is determined to be available, false otherwise

+/// \details HasSHA() is a runtime check performed using CPUID

+/// \note This function is only available on Intel IA-32 platforms

 inline bool HasSHA()

 {

 	if (!g_x86DetectionDone)

@@ -188,10 +188,10 @@ inline bool HasSHA()
 	return g_hasSHA;

 }

 

-//! \brief Determines ADX availability

-//! \returns true if ADX is determined to be available, false otherwise

-//! \details HasADX() is a runtime check performed using CPUID

-//! \note This function is only available on Intel IA-32 platforms

+/// \brief Determines ADX availability

+/// \returns true if ADX is determined to be available, false otherwise

+/// \details HasADX() is a runtime check performed using CPUID

+/// \note This function is only available on Intel IA-32 platforms

 inline bool HasADX()

 {

 	if (!g_x86DetectionDone)

@@ -199,10 +199,10 @@ inline bool HasADX()
 	return g_hasADX;

 }

 

-//! \brief Determines if the CPU is an Intel P4

-//! \returns true if the CPU is a P4, false otherwise

-//! \details IsP4() is a runtime check performed using CPUID

-//! \note This function is only available on Intel IA-32 platforms

+/// \brief Determines if the CPU is an Intel P4

+/// \returns true if the CPU is a P4, false otherwise

+/// \details IsP4() is a runtime check performed using CPUID

+/// \note This function is only available on Intel IA-32 platforms

 inline bool IsP4()

 {

 	if (!g_x86DetectionDone)

@@ -210,10 +210,10 @@ inline bool IsP4()
 	return g_isP4;

 }

 

-//! \brief Determines RDRAND availability

-//! \returns true if RDRAND is determined to be available, false otherwise

-//! \details HasRDRAND() is a runtime check performed using CPUID

-//! \note This function is only available on Intel IA-32 platforms

+/// \brief Determines RDRAND availability

+/// \returns true if RDRAND is determined to be available, false otherwise

+/// \details HasRDRAND() is a runtime check performed using CPUID

+/// \note This function is only available on Intel IA-32 platforms

 inline bool HasRDRAND()

 {

 	if (!g_x86DetectionDone)

@@ -221,10 +221,10 @@ inline bool HasRDRAND()
 	return g_hasRDRAND;

 }

 

-//! \brief Determines RDSEED availability

-//! \returns true if RDSEED is determined to be available, false otherwise

-//! \details HasRDSEED() is a runtime check performed using CPUID

-//! \note This function is only available on Intel IA-32 platforms

+/// \brief Determines RDSEED availability

+/// \returns true if RDSEED is determined to be available, false otherwise

+/// \details HasRDSEED() is a runtime check performed using CPUID

+/// \note This function is only available on Intel IA-32 platforms

 inline bool HasRDSEED()

 {

 	if (!g_x86DetectionDone)

@@ -232,10 +232,10 @@ inline bool HasRDSEED()
 	return g_hasRDSEED;

 }

 

-//! \brief Determines Padlock RNG availability

-//! \returns true if VIA Padlock RNG is determined to be available, false otherwise

-//! \details HasPadlockRNG() is a runtime check performed using CPUID

-//! \note This function is only available on Intel IA-32 platforms

+/// \brief Determines Padlock RNG availability

+/// \returns true if VIA Padlock RNG is determined to be available, false otherwise

+/// \details HasPadlockRNG() is a runtime check performed using CPUID

+/// \note This function is only available on Intel IA-32 platforms

 inline bool HasPadlockRNG()

 {

 	if (!g_x86DetectionDone)

@@ -243,10 +243,10 @@ inline bool HasPadlockRNG()
 	return g_hasPadlockRNG;

 }

 

-//! \brief Determines Padlock ACE availability

-//! \returns true if VIA Padlock ACE is determined to be available, false otherwise

-//! \details HasPadlockACE() is a runtime check performed using CPUID

-//! \note This function is only available on Intel IA-32 platforms

+/// \brief Determines Padlock ACE availability

+/// \returns true if VIA Padlock ACE is determined to be available, false otherwise

+/// \details HasPadlockACE() is a runtime check performed using CPUID

+/// \note This function is only available on Intel IA-32 platforms

 inline bool HasPadlockACE()

 {

 	if (!g_x86DetectionDone)

@@ -254,10 +254,10 @@ inline bool HasPadlockACE()
 	return g_hasPadlockACE;

 }

 

-//! \brief Determines Padlock ACE2 availability

-//! \returns true if VIA Padlock ACE2 is determined to be available, false otherwise

-//! \details HasPadlockACE2() is a runtime check performed using CPUID

-//! \note This function is only available on Intel IA-32 platforms

+/// \brief Determines Padlock ACE2 availability

+/// \returns true if VIA Padlock ACE2 is determined to be available, false otherwise

+/// \details HasPadlockACE2() is a runtime check performed using CPUID

+/// \note This function is only available on Intel IA-32 platforms

 inline bool HasPadlockACE2()

 {

 	if (!g_x86DetectionDone)

@@ -265,10 +265,10 @@ inline bool HasPadlockACE2()
 	return g_hasPadlockACE2;

 }

 

-//! \brief Determines Padlock PHE availability

-//! \returns true if VIA Padlock PHE is determined to be available, false otherwise

-//! \details HasPadlockPHE() is a runtime check performed using CPUID

-//! \note This function is only available on Intel IA-32 platforms

+/// \brief Determines Padlock PHE availability

+/// \returns true if VIA Padlock PHE is determined to be available, false otherwise

+/// \details HasPadlockPHE() is a runtime check performed using CPUID

+/// \note This function is only available on Intel IA-32 platforms

 inline bool HasPadlockPHE()

 {

 	if (!g_x86DetectionDone)

@@ -276,10 +276,10 @@ inline bool HasPadlockPHE()
 	return g_hasPadlockPHE;

 }

 

-//! \brief Determines Padlock PMM availability

-//! \returns true if VIA Padlock PMM is determined to be available, false otherwise

-//! \details HasPadlockPMM() is a runtime check performed using CPUID

-//! \note This function is only available on Intel IA-32 platforms

+/// \brief Determines Padlock PMM availability

+/// \returns true if VIA Padlock PMM is determined to be available, false otherwise

+/// \details HasPadlockPMM() is a runtime check performed using CPUID

+/// \note This function is only available on Intel IA-32 platforms

 inline bool HasPadlockPMM()

 {

 	if (!g_x86DetectionDone)

@@ -287,14 +287,14 @@ inline bool HasPadlockPMM()
 	return g_hasPadlockPMM;

 }

 

-//! \brief Provides the cache line size

-//! \returns lower bound on the size of a cache line in bytes, if available

-//! \details GetCacheLineSize() returns the lower bound on the size of a cache line, if it

-//!   is available. If the value is not available at runtime, then 32 is returned for a 32-bit

-//!   processor and 64 is returned for a 64-bit processor.

-//! \details x86/x32/x64 uses CPUID to determine the value and it is usually accurate. PowerPC

-//!   and AIX also makes the value available to user space and it is also usually accurate. The

-//!   ARM processor equivalent is a privileged instruction, so a compile time value is returned.

+/// \brief Provides the cache line size

+/// \returns lower bound on the size of a cache line in bytes, if available

+/// \details GetCacheLineSize() returns the lower bound on the size of a cache line, if it

+///   is available. If the value is not available at runtime, then 32 is returned for a 32-bit

+///   processor and 64 is returned for a 64-bit processor.

+/// \details x86/x32/x64 uses CPUID to determine the value and it is usually accurate. PowerPC

+///   and AIX also makes the value available to user space and it is also usually accurate. The

+///   ARM processor equivalent is a privileged instruction, so a compile time value is returned.

 inline int GetCacheLineSize()

 {

 	if (!g_x86DetectionDone)

@@ -316,16 +316,16 @@ extern bool g_hasNEON, g_hasPMULL, g_hasCRC32, g_hasAES, g_hasSHA1, g_hasSHA2;
 void CRYPTOPP_API DetectArmFeatures();

 #endif  // CRYPTOPP_DOXYGEN_PROCESSING

 

-//! \name ARM A-32, Aarch32 and AArch64 CPU FEATURES

+/// \name ARM A-32, Aarch32 and AArch64 CPU FEATURES

 //@{

 

-//! \brief Determine if an ARM processor has Advanced SIMD available

-//! \returns true if the hardware is capable of Advanced SIMD at runtime, false otherwise.

-//! \details Advanced SIMD instructions are available under most ARMv7, Aarch32 and Aarch64.

-//! \details Runtime support requires compile time support. When compiling with GCC, you may

-//!   need to compile with <tt>-mfpu=neon</tt> (32-bit) or <tt>-march=armv8-a</tt>

-//!   (64-bit). Also see ARM's <tt>__ARM_NEON</tt> preprocessor macro.

-//! \note This function is only available on ARM-32, Aarch32 and Aarch64 platforms

+/// \brief Determine if an ARM processor has Advanced SIMD available

+/// \returns true if the hardware is capable of Advanced SIMD at runtime, false otherwise.

+/// \details Advanced SIMD instructions are available under most ARMv7, Aarch32 and Aarch64.

+/// \details Runtime support requires compile time support. When compiling with GCC, you may

+///   need to compile with <tt>-mfpu=neon</tt> (32-bit) or <tt>-march=armv8-a</tt>

+///   (64-bit). Also see ARM's <tt>__ARM_NEON</tt> preprocessor macro.

+/// \note This function is only available on ARM-32, Aarch32 and Aarch64 platforms

 inline bool HasNEON()

 {

 	// ASIMD is a core feature on Aarch32 and Aarch64 like SSE2 is a core feature on x86_64

@@ -338,13 +338,13 @@ inline bool HasNEON()
 #endif

 }

 

-//! \brief Determine if an ARM processor provides Polynomial Multiplication

-//! \returns true if the hardware is capable of polynomial multiplications at runtime, false otherwise.

-//! \details The multiplication instructions are available under Aarch32 and Aarch64.

-//! \details Runtime support requires compile time support. When compiling with GCC, you may

-//!   need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires

-//!   <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.

-//! \note This function is only available on ARM-32, Aarch32 and Aarch64 platforms

+/// \brief Determine if an ARM processor provides Polynomial Multiplication

+/// \returns true if the hardware is capable of polynomial multiplications at runtime, false otherwise.

+/// \details The multiplication instructions are available under Aarch32 and Aarch64.

+/// \details Runtime support requires compile time support. When compiling with GCC, you may

+///   need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires

+///   <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.

+/// \note This function is only available on ARM-32, Aarch32 and Aarch64 platforms

 inline bool HasPMULL()

 {

 #if defined(__aarch32__) || defined(__aarch64__)

@@ -356,14 +356,14 @@ inline bool HasPMULL()
 #endif

 }

 

-//! \brief Determine if an ARM processor has CRC32 available

-//! \returns true if the hardware is capable of CRC32 at runtime, false otherwise.

-//! \details CRC32 instructions provide access to the processor's CRC-32 and CRC-32C instructions.

-//!   They are provided by ARM C Language Extensions 2.0 (ACLE 2.0) and available under Aarch32 and Aarch64.

-//! \details Runtime support requires compile time support. When compiling with GCC, you may

-//!   need to compile with <tt>-march=armv8-a+crc</tt>; while Apple requires

-//!   <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRC32</tt> preprocessor macro.

-//! \note This function is only available on ARM-32, Aarch32 and Aarch64 platforms

+/// \brief Determine if an ARM processor has CRC32 available

+/// \returns true if the hardware is capable of CRC32 at runtime, false otherwise.

+/// \details CRC32 instructions provide access to the processor's CRC-32 and CRC-32C instructions.

+///   They are provided by ARM C Language Extensions 2.0 (ACLE 2.0) and available under Aarch32 and Aarch64.

+/// \details Runtime support requires compile time support. When compiling with GCC, you may

+///   need to compile with <tt>-march=armv8-a+crc</tt>; while Apple requires

+///   <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRC32</tt> preprocessor macro.

+/// \note This function is only available on ARM-32, Aarch32 and Aarch64 platforms

 inline bool HasCRC32()

 {

 #if defined(__aarch32__) || defined(__aarch64__)

@@ -375,14 +375,14 @@ inline bool HasCRC32()
 #endif

 }

 

-//! \brief Determine if an ARM processor has AES available

-//! \returns true if the hardware is capable of AES at runtime, false otherwise.

-//! \details AES is part of the optional Crypto extensions on Aarch32 and Aarch64. They are

-//!   accessed using ARM C Language Extensions 2.0 (ACLE 2.0).

-//! \details Runtime support requires compile time support. When compiling with GCC, you may

-//!   need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires

-//!   <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.

-//! \note This function is only available on ARM-32, Aarch32 and Aarch64 platforms

+/// \brief Determine if an ARM processor has AES available

+/// \returns true if the hardware is capable of AES at runtime, false otherwise.

+/// \details AES is part of the optional Crypto extensions on Aarch32 and Aarch64. They are

+///   accessed using ARM C Language Extensions 2.0 (ACLE 2.0).

+/// \details Runtime support requires compile time support. When compiling with GCC, you may

+///   need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires

+///   <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.

+/// \note This function is only available on ARM-32, Aarch32 and Aarch64 platforms

 inline bool HasAES()

 {

 #if defined(__aarch32__) || defined(__aarch64__)

@@ -394,14 +394,14 @@ inline bool HasAES()
 #endif

 }

 

-//! \brief Determine if an ARM processor has SHA1 available

-//! \returns true if the hardware is capable of SHA1 at runtime, false otherwise.

-//! \details SHA1 is part of the optional Crypto extensions on Aarch32 and Aarch64. They are

-//!   accessed using ARM C Language Extensions 2.0 (ACLE 2.0).

-//! \details Runtime support requires compile time support. When compiling with GCC, you may

-//!   need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires

-//!   <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.

-//! \note This function is only available on ARM-32, Aarch32 and Aarch64 platforms

+/// \brief Determine if an ARM processor has SHA1 available

+/// \returns true if the hardware is capable of SHA1 at runtime, false otherwise.

+/// \details SHA1 is part of the optional Crypto extensions on Aarch32 and Aarch64. They are

+///   accessed using ARM C Language Extensions 2.0 (ACLE 2.0).

+/// \details Runtime support requires compile time support. When compiling with GCC, you may

+///   need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires

+///   <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.

+/// \note This function is only available on ARM-32, Aarch32 and Aarch64 platforms

 inline bool HasSHA1()

 {

 #if defined(__aarch32__) || defined(__aarch64__)

@@ -413,14 +413,14 @@ inline bool HasSHA1()
 #endif

 }

 

-//! \brief Determine if an ARM processor has SHA2 available

-//! \returns true if the hardware is capable of SHA2 at runtime, false otherwise.

-//! \details SHA2 is part of the optional Crypto extensions on Aarch32 and Aarch64. They are

-//!   accessed using ARM C Language Extensions 2.0 (ACLE 2.0).

-//! \details Runtime support requires compile time support. When compiling with GCC, you may

-//!   need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires

-//!   <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.

-//! \note This function is only available on ARM-32, Aarch32 and Aarch64 platforms

+/// \brief Determine if an ARM processor has SHA2 available

+/// \returns true if the hardware is capable of SHA2 at runtime, false otherwise.

+/// \details SHA2 is part of the optional Crypto extensions on Aarch32 and Aarch64. They are

+///   accessed using ARM C Language Extensions 2.0 (ACLE 2.0).

+/// \details Runtime support requires compile time support. When compiling with GCC, you may

+///   need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires

+///   <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.

+/// \note This function is only available on ARM-32, Aarch32 and Aarch64 platforms

 inline bool HasSHA2()

 {

 #if defined(__aarch32__) || defined(__aarch64__)

@@ -448,19 +448,19 @@ extern word32 g_cacheLineSize;
 void CRYPTOPP_API DetectPowerpcFeatures();

 #endif  // CRYPTOPP_DOXYGEN_PROCESSING

 

-//! \name POWERPC CPU FEATURES

+/// \name POWERPC CPU FEATURES

 //@{

 

-//! \brief Determine if a PowerPC processor has Altivec available

-//! \returns true if the hardware is capable of Altivec at runtime, false otherwise.

-//! \details Altivec instructions are available under most modern PowerPCs.

-//! \details Runtime support requires compile time support. When compiling with GCC, you may

-//!   need to compile with <tt>-mcpu=power7</tt>; while IBM XL C/C++ compilers require

-//!   <tt>-qarch=pwr7 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro.

-//! \details Atilvec was first available on Power4 platforms. However Crypto++ releies on unaligned

-//!   loads and stores which is a Power7 feature. If the platform lacks Power7 extensions, then the

-//!   GNUmakefile sets <tt>-DCRYPTOPP_DISABLE_ALTIVEC</tt>.

-//! \note This function is only available on PowerPC and PowerPC-64 platforms

+/// \brief Determine if a PowerPC processor has Altivec available

+/// \returns true if the hardware is capable of Altivec at runtime, false otherwise.

+/// \details Altivec instructions are available under most modern PowerPCs.

+/// \details Runtime support requires compile time support. When compiling with GCC, you may

+///   need to compile with <tt>-mcpu=power7</tt>; while IBM XL C/C++ compilers require

+///   <tt>-qarch=pwr7 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro.

+/// \details Atilvec was first available on Power4 platforms. However Crypto++ releies on unaligned

+///   loads and stores which is a Power7 feature. If the platform lacks Power7 extensions, then the

+///   GNUmakefile sets <tt>-DCRYPTOPP_DISABLE_ALTIVEC</tt>.

+/// \note This function is only available on PowerPC and PowerPC-64 platforms

 inline bool HasAltivec()

 {

 	if (!g_PowerpcDetectionDone)

@@ -468,16 +468,16 @@ inline bool HasAltivec()
 	return g_hasAltivec;

 }

 

-//! \brief Determine if a PowerPC processor has Power8 available

-//! \returns true if the hardware is capable of Power8 at runtime, false otherwise.

-//! \details Altivec instructions are available under most modern PowerPCs.

-//! \details Runtime support requires compile time support. When compiling with GCC, you may

-//!   need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require

-//!   <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro.

-//! \details Atilvec was first available on Power4 platforms. However Crypto++ releies on unaligned

-//!   loads and stores which is a Power7 feature. If the platform lacks Power7 extensions, then the

-//!   GNUmakefile sets <tt>-DCRYPTOPP_DISABLE_ALTIVEC</tt>.

-//! \note This function is only available on PowerPC and PowerPC-64 platforms

+/// \brief Determine if a PowerPC processor has Power8 available

+/// \returns true if the hardware is capable of Power8 at runtime, false otherwise.

+/// \details Altivec instructions are available under most modern PowerPCs.

+/// \details Runtime support requires compile time support. When compiling with GCC, you may

+///   need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require

+///   <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro.

+/// \details Atilvec was first available on Power4 platforms. However Crypto++ releies on unaligned

+///   loads and stores which is a Power7 feature. If the platform lacks Power7 extensions, then the

+///   GNUmakefile sets <tt>-DCRYPTOPP_DISABLE_ALTIVEC</tt>.

+/// \note This function is only available on PowerPC and PowerPC-64 platforms

 inline bool HasPower7()

 {

 	if (!g_PowerpcDetectionDone)

@@ -485,16 +485,16 @@ inline bool HasPower7()
 	return g_hasPower7;

 }

 

-//! \brief Determine if a PowerPC processor has Power8 available

-//! \returns true if the hardware is capable of Power8 at runtime, false otherwise.

-//! \details Altivec instructions are available under most modern PowerPCs.

-//! \details Runtime support requires compile time support. When compiling with GCC, you may

-//!   need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require

-//!   <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro.

-//! \details Atilvec was first available on Power4 platforms. However Crypto++ releies on unaligned

-//!   loads and stores which is a Power7 feature. If the platform lacks Power7 extensions, then the

-//!   GNUmakefile sets <tt>-DCRYPTOPP_DISABLE_ALTIVEC</tt>.

-//! \note This function is only available on PowerPC and PowerPC-64 platforms

+/// \brief Determine if a PowerPC processor has Power8 available

+/// \returns true if the hardware is capable of Power8 at runtime, false otherwise.

+/// \details Altivec instructions are available under most modern PowerPCs.

+/// \details Runtime support requires compile time support. When compiling with GCC, you may

+///   need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require

+///   <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro.

+/// \details Atilvec was first available on Power4 platforms. However Crypto++ releies on unaligned

+///   loads and stores which is a Power7 feature. If the platform lacks Power7 extensions, then the

+///   GNUmakefile sets <tt>-DCRYPTOPP_DISABLE_ALTIVEC</tt>.

+/// \note This function is only available on PowerPC and PowerPC-64 platforms

 inline bool HasPower8()

 {

 	if (!g_PowerpcDetectionDone)

@@ -502,13 +502,13 @@ inline bool HasPower8()
 	return g_hasPower8;

 }

 

-//! \brief Determine if a PowerPC processor has AES available

-//! \returns true if the hardware is capable of AES at runtime, false otherwise.

-//! \details AES is part of the in-crypto extensions on Power8 and Power9.

-//! \details Runtime support requires compile time support. When compiling with GCC, you may

-//!   need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require

-//!   <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>__CRYPTO</tt> preprocessor macro.

-//! \note This function is only available on PowerPC and PowerPC-64 platforms

+/// \brief Determine if a PowerPC processor has AES available

+/// \returns true if the hardware is capable of AES at runtime, false otherwise.

+/// \details AES is part of the in-crypto extensions on Power8 and Power9.

+/// \details Runtime support requires compile time support. When compiling with GCC, you may

+///   need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require

+///   <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>__CRYPTO</tt> preprocessor macro.

+/// \note This function is only available on PowerPC and PowerPC-64 platforms

 inline bool HasAES()

 {

 	if (!g_PowerpcDetectionDone)

@@ -516,13 +516,13 @@ inline bool HasAES()
 	return g_hasAES;

 }

 

-//! \brief Determine if a PowerPC processor has SHA256 available

-//! \returns true if the hardware is capable of SHA256 at runtime, false otherwise.

-//! \details SHA is part of the in-crypto extensions on Power8 and Power9.

-//! \details Runtime support requires compile time support. When compiling with GCC, you may

-//!   need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require

-//!   <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>__CRYPTO</tt> preprocessor macro.

-//! \note This function is only available on PowerPC and PowerPC-64 platforms

+/// \brief Determine if a PowerPC processor has SHA256 available

+/// \returns true if the hardware is capable of SHA256 at runtime, false otherwise.

+/// \details SHA is part of the in-crypto extensions on Power8 and Power9.

+/// \details Runtime support requires compile time support. When compiling with GCC, you may

+///   need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require

+///   <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>__CRYPTO</tt> preprocessor macro.

+/// \note This function is only available on PowerPC and PowerPC-64 platforms

 inline bool HasSHA256()

 {

 	if (!g_PowerpcDetectionDone)

@@ -530,13 +530,13 @@ inline bool HasSHA256()
 	return g_hasSHA256;

 }

 

-//! \brief Determine if a PowerPC processor has SHA512 available

-//! \returns true if the hardware is capable of SHA512 at runtime, false otherwise.

-//! \details SHA is part of the in-crypto extensions on Power8 and Power9.

-//! \details Runtime support requires compile time support. When compiling with GCC, you may

-//!   need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require

-//!   <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>__CRYPTO</tt> preprocessor macro.

-//! \note This function is only available on PowerPC and PowerPC-64 platforms

+/// \brief Determine if a PowerPC processor has SHA512 available

+/// \returns true if the hardware is capable of SHA512 at runtime, false otherwise.

+/// \details SHA is part of the in-crypto extensions on Power8 and Power9.

+/// \details Runtime support requires compile time support. When compiling with GCC, you may

+///   need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require

+///   <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>__CRYPTO</tt> preprocessor macro.

+/// \note This function is only available on PowerPC and PowerPC-64 platforms

 inline bool HasSHA512()

 {

 	if (!g_PowerpcDetectionDone)

@@ -544,14 +544,14 @@ inline bool HasSHA512()
 	return g_hasSHA512;

 }

 

-//! \brief Provides the cache line size

-//! \returns lower bound on the size of a cache line in bytes, if available

-//! \details GetCacheLineSize() returns the lower bound on the size of a cache line, if it

-//!   is available. If the value is not available at runtime, then 32 is returned for a 32-bit

-//!   processor and 64 is returned for a 64-bit processor.

-//! \details x86/x32/x64 uses CPUID to determine the value and it is usually accurate. PowerPC

-//!   and AIX also makes the value available to user space and it is also usually accurate. The

-//!   ARM processor equivalent is a privileged instruction, so a compile time value is returned.

+/// \brief Provides the cache line size

+/// \returns lower bound on the size of a cache line in bytes, if available

+/// \details GetCacheLineSize() returns the lower bound on the size of a cache line, if it

+///   is available. If the value is not available at runtime, then 32 is returned for a 32-bit

+///   processor and 64 is returned for a 64-bit processor.

+/// \details x86/x32/x64 uses CPUID to determine the value and it is usually accurate. PowerPC

+///   and AIX also makes the value available to user space and it is also usually accurate. The

+///   ARM processor equivalent is a privileged instruction, so a compile time value is returned.

 inline int GetCacheLineSize()

 {

 	if (!g_PowerpcDetectionDone)

@@ -567,14 +567,14 @@ inline int GetCacheLineSize()
 

 // Non-Intel systems

 #if !(CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64 || CRYPTOPP_BOOL_PPC32 || CRYPTOPP_BOOL_PPC64)

-//! \brief Provides the cache line size

-//! \returns lower bound on the size of a cache line in bytes, if available

-//! \details GetCacheLineSize() returns the lower bound on the size of a cache line, if it

-//!   is available. If the value is not available at runtime, then 32 is returned for a 32-bit

-//!   processor and 64 is returned for a 64-bit processor.

-//! \details x86/x32/x64 uses CPUID to determine the value and it is usually accurate. PowerPC

-//!   and AIX also makes the value available to user space and it is also usually accurate. The

-//!   ARM processor equivalent is a privileged instruction, so a compile time value is returned.

+/// \brief Provides the cache line size

+/// \returns lower bound on the size of a cache line in bytes, if available

+/// \details GetCacheLineSize() returns the lower bound on the size of a cache line, if it

+///   is available. If the value is not available at runtime, then 32 is returned for a 32-bit

+///   processor and 64 is returned for a 64-bit processor.

+/// \details x86/x32/x64 uses CPUID to determine the value and it is usually accurate. PowerPC

+///   and AIX also makes the value available to user space and it is also usually accurate. The

+///   ARM processor equivalent is a privileged instruction, so a compile time value is returned.

 inline int GetCacheLineSize()

 {

 	return CRYPTOPP_L1_CACHE_LINE_SIZE;