Whitespace check-in

1 files changed, 77 insertions, 77 deletions

diff --git a/cpu.h b/cpu.h
index b2dd0ab1..763ef5c9 100644
--- a/cpu.h
+++ b/cpu.h
@@ -5,27 +5,27 @@
 /// \file cpu.h

 /// \brief Functions for CPU features and intrinsics

 /// \details The CPU functions are used in IA-32, ARM and PowerPC code paths. The

-///   functions provide cpu specific feature testing on IA-32, ARM and PowerPC machines.

+///  functions provide cpu specific feature testing on IA-32, ARM and PowerPC machines.

 /// \details Feature detection uses CPUID on IA-32, like Intel and AMD. On other platforms

-///   a two-part strategy is used. First, the library attempts to *Query* the OS for a feature,

-///   like using Linux getauxval() or android_getCpuFeatures(). If that fails, then *Probe*

-///   the cpu executing an instruction and an observe a SIGILL if unsupported. The general

-///   pattern used by the library is:

+///  a two-part strategy is used. First, the library attempts to *Query* the OS for a feature,

+///  like using Linux getauxval() or android_getCpuFeatures(). If that fails, then *Probe*

+///  the cpu executing an instruction and an observe a SIGILL if unsupported. The general

+///  pattern used by the library is:

 /// <pre>

-///     g_hasCRC32 = CPU_QueryCRC32() || CPU_ProbeCRC32();

-///     g_hasPMULL = CPU_QueryPMULL() || CPU_ProbePMULL();

-///     g_hasAES  = CPU_QueryAES() || CPU_ProbeAES();

+///    g_hasCRC32 = CPU_QueryCRC32() || CPU_ProbeCRC32();

+///    g_hasPMULL = CPU_QueryPMULL() || CPU_ProbePMULL();

+///    g_hasAES  = CPU_QueryAES() || CPU_ProbeAES();

 /// </pre>

 /// \details Generally speaking, CPU_Query() is in the source file <tt>cpu.cpp</tt> because it

-///   does not require special architectural flags. CPU_Probe() is in a source file that recieves

-///   architectural flags, like <tt>sse_simd.cpp</tt>, <tt>neon_simd.cpp</tt> and

-///   <tt>ppc_simd.cpp</tt>. For example, compiling <tt>neon_simd.cpp</tt> on an ARM64 machine will

-///   have <tt>-march=armv8-a</tt> applied during a compile to make the instruction set architecture

-///   (ISA) available.

+///  does not require special architectural flags. CPU_Probe() is in a source file that recieves

+///  architectural flags, like <tt>sse_simd.cpp</tt>, <tt>neon_simd.cpp</tt> and

+///  <tt>ppc_simd.cpp</tt>. For example, compiling <tt>neon_simd.cpp</tt> on an ARM64 machine will

+///  have <tt>-march=armv8-a</tt> applied during a compile to make the instruction set architecture

+///  (ISA) available.

 /// \details The cpu probes are expensive when compared to a standard OS feature query. The library

-///   also avoids probes on Apple platforms because Apple's signal handling for SIGILLs appears to

-///   corrupt memory. CPU_Probe() will unconditionally return false for Apple platforms. OpenSSL

-///   experienced the same problem and moved away from SIGILL probes on Apple.

+///  also avoids probes on Apple platforms because Apple's signal handling for SIGILLs appears to

+///  corrupt memory. CPU_Probe() will unconditionally return false for Apple platforms. OpenSSL

+///  experienced the same problem and moved away from SIGILL probes on Apple.

 

 #ifndef CRYPTOPP_CPU_H

 #define CRYPTOPP_CPU_H

@@ -111,7 +111,7 @@ CRYPTOPP_DLL bool CRYPTOPP_API CpuId(word32 func, word32 subfunc, word32 output[
 /// \brief Determines SSE2 availability

 /// \returns true if SSE2 is determined to be available, false otherwise

 /// \details MMX, SSE and SSE2 are core processor features for x86_64, and

-///   the function always returns true for the platform.

+///  the function always returns true for the platform.

 /// \note This function is only available on Intel IA-32 platforms

 inline bool HasSSE2()

 {

@@ -384,11 +384,11 @@ inline bool IsP4()
 /// \brief Provides the cache line size

 /// \returns lower bound on the size of a cache line in bytes, if available

 /// \details GetCacheLineSize() returns the lower bound on the size of a cache line, if it

-///   is available. If the value is not available at runtime, then 32 is returned for a 32-bit

-///   processor and 64 is returned for a 64-bit processor.

+///  is available. If the value is not available at runtime, then 32 is returned for a 32-bit

+///  processor and 64 is returned for a 64-bit processor.

 /// \details x86/x32/x64 uses CPUID to determine the value and it is usually accurate. PowerPC

-///   and AIX also makes the value available to user space and it is also usually accurate. The

-///   ARM processor equivalent is a privileged instruction, so a compile time value is returned.

+///  and AIX also makes the value available to user space and it is also usually accurate. The

+///  ARM processor equivalent is a privileged instruction, so a compile time value is returned.

 inline int GetCacheLineSize()

 {

 	if (!g_x86DetectionDone)

@@ -444,8 +444,8 @@ inline bool HasARMv7()
 /// \returns true if the hardware is capable of Advanced SIMD at runtime, false otherwise.

 /// \details Advanced SIMD instructions are available under most ARMv7, Aarch32 and Aarch64.

 /// \details Runtime support requires compile time support. When compiling with GCC, you may

-///   need to compile with <tt>-mfpu=neon</tt> (32-bit) or <tt>-march=armv8-a</tt>

-///   (64-bit). Also see ARM's <tt>__ARM_NEON</tt> preprocessor macro.

+///  need to compile with <tt>-mfpu=neon</tt> (32-bit) or <tt>-march=armv8-a</tt>

+///  (64-bit). Also see ARM's <tt>__ARM_NEON</tt> preprocessor macro.

 /// \since Crypto++ 5.6.4

 /// \note This function is only available on ARM-32, Aarch32 and Aarch64 platforms

 inline bool HasNEON()

@@ -462,11 +462,11 @@ inline bool HasNEON()
 

 /// \brief Determine if an ARM processor provides Polynomial Multiplication

 /// \returns true if the hardware is capable of polynomial multiplications at runtime,

-///   false otherwise.

+///  false otherwise.

 /// \details The multiplication instructions are available under Aarch32 and Aarch64.

 /// \details Runtime support requires compile time support. When compiling with GCC,

-///   you may need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires

-///   <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.

+///  you may need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires

+///  <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.

 /// \since Crypto++ 5.6.4

 /// \note This function is only available on Aarch32 and Aarch64 platforms

 inline bool HasPMULL()

@@ -483,11 +483,11 @@ inline bool HasPMULL()
 /// \brief Determine if an ARM processor has CRC32 available

 /// \returns true if the hardware is capable of CRC32 at runtime, false otherwise.

 /// \details CRC32 instructions provide access to the processor's CRC-32 and CRC-32C

-///   instructions. They are provided by ARM C Language Extensions 2.0 (ACLE 2.0) and

-///   available under Aarch32 and Aarch64.

+///  instructions. They are provided by ARM C Language Extensions 2.0 (ACLE 2.0) and

+///  available under Aarch32 and Aarch64.

 /// \details Runtime support requires compile time support. When compiling with GCC,

-///   you may need to compile with <tt>-march=armv8-a+crc</tt>; while Apple requires

-///   <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRC32</tt> preprocessor macro.

+///  you may need to compile with <tt>-march=armv8-a+crc</tt>; while Apple requires

+///  <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRC32</tt> preprocessor macro.

 /// \since Crypto++ 5.6.4

 /// \note This function is only available on Aarch32 and Aarch64 platforms

 inline bool HasCRC32()

@@ -504,10 +504,10 @@ inline bool HasCRC32()
 /// \brief Determine if an ARM processor has AES available

 /// \returns true if the hardware is capable of AES at runtime, false otherwise.

 /// \details AES is part of the optional Crypto extensions on Aarch32 and Aarch64. They are

-///   accessed using ARM C Language Extensions 2.0 (ACLE 2.0).

+///  accessed using ARM C Language Extensions 2.0 (ACLE 2.0).

 /// \details Runtime support requires compile time support. When compiling with GCC, you may

-///   need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires

-///   <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.

+///  need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires

+///  <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.

 /// \since Crypto++ 5.6.4

 /// \note This function is only available on Aarch32 and Aarch64 platforms

 inline bool HasAES()

@@ -524,10 +524,10 @@ inline bool HasAES()
 /// \brief Determine if an ARM processor has SHA1 available

 /// \returns true if the hardware is capable of SHA1 at runtime, false otherwise.

 /// \details SHA1 is part of the optional Crypto extensions on Aarch32 and Aarch64. They are

-///   accessed using ARM C Language Extensions 2.0 (ACLE 2.0).

+///  accessed using ARM C Language Extensions 2.0 (ACLE 2.0).

 /// \details Runtime support requires compile time support. When compiling with GCC, you may

-///   need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires

-///   <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.

+///  need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires

+///  <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.

 /// \since Crypto++ 5.6.4

 /// \note This function is only available on Aarch32 and Aarch64 platforms

 inline bool HasSHA1()

@@ -544,10 +544,10 @@ inline bool HasSHA1()
 /// \brief Determine if an ARM processor has SHA256 available

 /// \returns true if the hardware is capable of SHA256 at runtime, false otherwise.

 /// \details SHA256 is part of the optional Crypto extensions on Aarch32 and Aarch64. They are

-///   accessed using ARM C Language Extensions 2.0 (ACLE 2.0).

+///  accessed using ARM C Language Extensions 2.0 (ACLE 2.0).

 /// \details Runtime support requires compile time support. When compiling with GCC, you may

-///   need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires

-///   <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.

+///  need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires

+///  <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.

 /// \since Crypto++ 5.6.4

 /// \note This function is only available on Aarch32 and Aarch64 platforms

 inline bool HasSHA2()

@@ -564,10 +564,10 @@ inline bool HasSHA2()
 /// \brief Determine if an ARM processor has SHA512 available

 /// \returns true if the hardware is capable of SHA512 at runtime, false otherwise.

 /// \details SHA512 is part of the ARMv8.4 Crypto extensions on Aarch32 and Aarch64. They

-///   are accessed using ARM C Language Extensions 2.0 (ACLE 2.0).

+///  are accessed using ARM C Language Extensions 2.0 (ACLE 2.0).

 /// \details Runtime support requires compile time support. When compiling with GCC, you

-///   may need to compile with <tt>-march=armv8.4-a+crypto</tt>; while Apple requires

-///   <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.

+///  may need to compile with <tt>-march=armv8.4-a+crypto</tt>; while Apple requires

+///  <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.

 /// \since Crypto++ 8.0

 /// \note This function is only available on Aarch32 and Aarch64 platforms

 inline bool HasSHA512()

@@ -584,10 +584,10 @@ inline bool HasSHA512()
 /// \brief Determine if an ARM processor has SHA3 available

 /// \returns true if the hardware is capable of SHA3 at runtime, false otherwise.

 /// \details SHA3 is part of the ARMv8.4 Crypto extensions on Aarch32 and Aarch64. They

-///   are accessed using ARM C Language Extensions 2.0 (ACLE 2.0).

+///  are accessed using ARM C Language Extensions 2.0 (ACLE 2.0).

 /// \details Runtime support requires compile time support. When compiling with GCC, you

-///   may need to compile with <tt>-march=armv8.4-a+crypto</tt>; while Apple requires

-///   <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.

+///  may need to compile with <tt>-march=armv8.4-a+crypto</tt>; while Apple requires

+///  <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.

 /// \since Crypto++ 8.0

 /// \note This function is only available on Aarch32 and Aarch64 platforms

 inline bool HasSHA3()

@@ -604,10 +604,10 @@ inline bool HasSHA3()
 /// \brief Determine if an ARM processor has SM3 available

 /// \returns true if the hardware is capable of SM3 at runtime, false otherwise.

 /// \details SM3 is part of the ARMv8.4 Crypto extensions on Aarch32 and Aarch64. They

-///   are accessed using ARM C Language Extensions 2.0 (ACLE 2.0).

+///  are accessed using ARM C Language Extensions 2.0 (ACLE 2.0).

 /// \details Runtime support requires compile time support. When compiling with GCC, you

-///   may need to compile with <tt>-march=armv8.4-a+crypto</tt>; while Apple requires

-///   <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.

+///  may need to compile with <tt>-march=armv8.4-a+crypto</tt>; while Apple requires

+///  <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.

 /// \since Crypto++ 8.0

 /// \note This function is only available on Aarch32 and Aarch64 platforms

 inline bool HasSM3()

@@ -624,10 +624,10 @@ inline bool HasSM3()
 /// \brief Determine if an ARM processor has SM4 available

 /// \returns true if the hardware is capable of SM4 at runtime, false otherwise.

 /// \details SM4 is part of the ARMv8.4 Crypto extensions on Aarch32 and Aarch64. They

-///   are accessed using ARM C Language Extensions 2.0 (ACLE 2.0).

+///  are accessed using ARM C Language Extensions 2.0 (ACLE 2.0).

 /// \details Runtime support requires compile time support. When compiling with GCC, you

-///   may need to compile with <tt>-march=armv8.4-a+crypto</tt>; while Apple requires

-///   <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.

+///  may need to compile with <tt>-march=armv8.4-a+crypto</tt>; while Apple requires

+///  <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.

 /// \since Crypto++ 8.0

 /// \note This function is only available on Aarch32 and Aarch64 platforms

 inline bool HasSM4()

@@ -672,8 +672,8 @@ void CRYPTOPP_API DetectPowerpcFeatures();
 /// \returns true if the hardware is capable of Altivec at runtime, false otherwise.

 /// \details Altivec instructions are available on modern PowerPCs.

 /// \details Runtime support requires compile time support. When compiling with GCC, you may

-///   need to compile with <tt>-mcpu=power4</tt>; while IBM XL C/C++ compilers require

-///   <tt>-qarch=pwr6 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro.

+///  need to compile with <tt>-mcpu=power4</tt>; while IBM XL C/C++ compilers require

+///  <tt>-qarch=pwr6 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro.

 /// \note This function is only available on PowerPC and PowerPC-64 platforms

 inline bool HasAltivec()

 {

@@ -689,8 +689,8 @@ inline bool HasAltivec()
 /// \brief Determine if a PowerPC processor has Power7 available

 /// \returns true if the hardware is capable of Power7 at runtime, false otherwise.

 /// \details Runtime support requires compile time support. When compiling with GCC, you may

-///   need to compile with <tt>-mcpu=power7</tt>; while IBM XL C/C++ compilers require

-///   <tt>-qarch=pwr7 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro.

+///  need to compile with <tt>-mcpu=power7</tt>; while IBM XL C/C++ compilers require

+///  <tt>-qarch=pwr7 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro.

 /// \note This function is only available on PowerPC and PowerPC-64 platforms

 inline bool HasPower7()

 {

@@ -706,8 +706,8 @@ inline bool HasPower7()
 /// \brief Determine if a PowerPC processor has Power8 available

 /// \returns true if the hardware is capable of Power8 at runtime, false otherwise.

 /// \details Runtime support requires compile time support. When compiling with GCC, you may

-///   need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require

-///   <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro.

+///  need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require

+///  <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro.

 /// \note This function is only available on PowerPC and PowerPC-64 platforms

 inline bool HasPower8()

 {

@@ -723,8 +723,8 @@ inline bool HasPower8()
 /// \brief Determine if a PowerPC processor has Power9 available

 /// \returns true if the hardware is capable of Power9 at runtime, false otherwise.

 /// \details Runtime support requires compile time support. When compiling with GCC, you may

-///   need to compile with <tt>-mcpu=power9</tt>; while IBM XL C/C++ compilers require

-///   <tt>-qarch=pwr9 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro.

+///  need to compile with <tt>-mcpu=power9</tt>; while IBM XL C/C++ compilers require

+///  <tt>-qarch=pwr9 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro.

 /// \note This function is only available on PowerPC and PowerPC-64 platforms

 inline bool HasPower9()

 {

@@ -741,8 +741,8 @@ inline bool HasPower9()
 /// \returns true if the hardware is capable of AES at runtime, false otherwise.

 /// \details AES is part of the in-crypto extensions on Power8 and Power9.

 /// \details Runtime support requires compile time support. When compiling with GCC, you may

-///   need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require

-///   <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>__CRYPTO</tt> preprocessor macro.

+///  need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require

+///  <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>__CRYPTO</tt> preprocessor macro.

 /// \note This function is only available on PowerPC and PowerPC-64 platforms

 inline bool HasAES()

 {

@@ -759,8 +759,8 @@ inline bool HasAES()
 /// \returns true if the hardware is capable of PMULL at runtime, false otherwise.

 /// \details PMULL is part of the in-crypto extensions on Power8 and Power9.

 /// \details Runtime support requires compile time support. When compiling with GCC, you may

-///   need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require

-///   <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>__CRYPTO</tt> preprocessor macro.

+///  need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require

+///  <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>__CRYPTO</tt> preprocessor macro.

 /// \note This function is only available on PowerPC and PowerPC-64 platforms

 inline bool HasPMULL()

 {

@@ -777,8 +777,8 @@ inline bool HasPMULL()
 /// \returns true if the hardware is capable of SHA256 at runtime, false otherwise.

 /// \details SHA is part of the in-crypto extensions on Power8 and Power9.

 /// \details Runtime support requires compile time support. When compiling with GCC, you may

-///   need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require

-///   <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>__CRYPTO</tt> preprocessor macro.

+///  need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require

+///  <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>__CRYPTO</tt> preprocessor macro.

 /// \note This function is only available on PowerPC and PowerPC-64 platforms

 inline bool HasSHA256()

 {

@@ -795,8 +795,8 @@ inline bool HasSHA256()
 /// \returns true if the hardware is capable of SHA512 at runtime, false otherwise.

 /// \details SHA is part of the in-crypto extensions on Power8 and Power9.

 /// \details Runtime support requires compile time support. When compiling with GCC, you may

-///   need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require

-///   <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>__CRYPTO</tt> preprocessor macro.

+///  need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require

+///  <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>__CRYPTO</tt> preprocessor macro.

 /// \note This function is only available on PowerPC and PowerPC-64 platforms

 inline bool HasSHA512()

 {

@@ -812,8 +812,8 @@ inline bool HasSHA512()
 /// \brief Determine if a PowerPC processor has DARN available

 /// \returns true if the hardware is capable of DARN at runtime, false otherwise.

 /// \details Runtime support requires compile time support. When compiling with GCC, you may

-///   need to compile with <tt>-mcpu=power9</tt>; while IBM XL C/C++ compilers require

-///   <tt>-qarch=pwr9 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro.

+///  need to compile with <tt>-mcpu=power9</tt>; while IBM XL C/C++ compilers require

+///  <tt>-qarch=pwr9 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro.

 /// \note This function is only available on PowerPC and PowerPC-64 platforms

 inline bool HasDARN()

 {

@@ -834,11 +834,11 @@ inline bool HasDARN()
 /// \brief Provides the cache line size

 /// \returns lower bound on the size of a cache line in bytes, if available

 /// \details GetCacheLineSize() returns the lower bound on the size of a cache line, if it

-///   is available. If the value is not available at runtime, then 32 is returned for a 32-bit

-///   processor and 64 is returned for a 64-bit processor.

+///  is available. If the value is not available at runtime, then 32 is returned for a 32-bit

+///  processor and 64 is returned for a 64-bit processor.

 /// \details x86/x32/x64 uses CPUID to determine the value and it is usually accurate. PowerPC

-///   and AIX also makes the value available to user space and it is also usually accurate. The

-///   ARM processor equivalent is a privileged instruction, so a compile time value is returned.

+///  and AIX also makes the value available to user space and it is also usually accurate. The

+///  ARM processor equivalent is a privileged instruction, so a compile time value is returned.

 inline int GetCacheLineSize()

 {

 	if (!g_PowerpcDetectionDone)

@@ -857,11 +857,11 @@ inline int GetCacheLineSize()
 /// \brief Provides the cache line size

 /// \returns lower bound on the size of a cache line in bytes, if available

 /// \details GetCacheLineSize() returns the lower bound on the size of a cache line, if it

-///   is available. If the value is not available at runtime, then 32 is returned for a 32-bit

-///   processor and 64 is returned for a 64-bit processor.

+///  is available. If the value is not available at runtime, then 32 is returned for a 32-bit

+///  processor and 64 is returned for a 64-bit processor.

 /// \details x86/x32/x64 uses CPUID to determine the value and it is usually accurate. PowerPC

-///   and AIX also makes the value available to user space and it is also usually accurate. The

-///   ARM processor equivalent is a privileged instruction, so a compile time value is returned.

+///  and AIX also makes the value available to user space and it is also usually accurate. The

+///  ARM processor equivalent is a privileged instruction, so a compile time value is returned.

 inline int GetCacheLineSize()

 {

 	return CRYPTOPP_L1_CACHE_LINE_SIZE;