summaryrefslogtreecommitdiff
path: root/chip/ish
diff options
context:
space:
mode:
Diffstat (limited to 'chip/ish')
-rw-r--r--chip/ish/aontaskfw/ish_aontask.c73
-rw-r--r--chip/ish/clock.c2
-rw-r--r--chip/ish/dma.c42
-rw-r--r--chip/ish/hbm.h6
-rw-r--r--chip/ish/heci_client.h6
-rw-r--r--chip/ish/hid_device.h6
-rw-r--r--chip/ish/hwtimer.c2
-rw-r--r--chip/ish/i2c.c6
-rw-r--r--chip/ish/ipc_heci.c10
-rw-r--r--chip/ish/ipc_heci.h2
-rw-r--r--chip/ish/ish_dma.h41
-rw-r--r--chip/ish/ish_i2c.h3
-rw-r--r--chip/ish/ish_persistent_data.c4
-rw-r--r--chip/ish/power_mgt.c34
-rw-r--r--chip/ish/power_mgt.h4
-rw-r--r--chip/ish/registers.h78
-rw-r--r--chip/ish/system_state_subsys.c2
-rw-r--r--chip/ish/uart.c11
-rw-r--r--chip/ish/uart_defs.h5
-rw-r--r--chip/ish/watchdog.c2
20 files changed, 80 insertions, 259 deletions
diff --git a/chip/ish/aontaskfw/ish_aontask.c b/chip/ish/aontaskfw/ish_aontask.c
index 6f2d9c9f2d..d167f3f5df 100644
--- a/chip/ish/aontaskfw/ish_aontask.c
+++ b/chip/ish/aontaskfw/ish_aontask.c
@@ -45,8 +45,8 @@
#include "common.h"
#include "ia_structs.h"
-#include "ish_aon_defs.h"
#include "ish_aon_share.h"
+#include "ish_aon_defs.h"
#include "ish_dma.h"
#include "power_mgt.h"
@@ -91,56 +91,6 @@
static void handle_reset(enum ish_pm_state pm_state);
-#if defined(CHIP_VARIANT_ISH5P4)
-static void sb_upstream_write_raw_base(uint32_t addr, uint32_t attr,
- uint32_t data, uint32_t sairs,
- uint8_t addr48, uint16_t addr_hi)
-{
- uint32_t eflags;
- uint32_t addr_hi_32;
-
- addr_hi_32 = addr_hi | (1 << 31);
-
- eflags = interrupt_lock();
-
- PMU_VNN_REQ = (1 << VNN_ID_SIDEBAND);
- while (!(PMU_VNN_REQ_ACK & PMU_VNN_REQ_ACK_STATUS))
- continue;
-
- if (dma_poll(SBEP_REG_UP_MSG_STATUS_ADDR, 0, UP_STATUS_BUSY_MASK) ==
- DMA_RC_OK) {
- SBEP_REG_UP_MSG_REQ_ADDR_LOW = addr;
-
- if (addr48) {
- SBEP_REG_UP_MSG_REQ_ADDR_HIGH = addr_hi_32;
- } else {
- SBEP_REG_UP_MSG_REQ_ADDR_HIGH = 0;
- }
-
- SBEP_REG_UP_MSG_REQ_ATTR = attr;
- SBEP_REG_UP_MSG_REQ_DATA = data;
- SBEP_REG_UP_MSG_REQ_EH = sairs;
- SBEP_REG_UP_MSG_COMMAND = SBEP_CMD_WRITE;
-
- dma_poll(SBEP_REG_UP_MSG_STATUS_ADDR, 0, UP_STATUS_BUSY_MASK);
- dma_poll(SBEP_REG_UP_MSG_STATUS_ADDR, UP_STATUS_MSG_SENT_MASK,
- UP_STATUS_MSG_SENT_MASK);
- SBEP_REG_UP_MSG_STATUS = UP_STATUS_MSG_SENT_CLR;
- }
-
- PMU_VNN_REQ = (1 << VNN_ID_SIDEBAND);
- interrupt_unlock(eflags);
-}
-
-static void sb_upstream_write_raw(uint32_t addr, uint32_t attr, uint32_t data,
- uint32_t sairs)
-{
- addr = addr & 0x0000FFFF;
-
- sb_upstream_write_raw_base(addr, attr, data, sairs, 0, 0);
-}
-#endif
-
/* ISR for PMU wakeup interrupt */
static void pmu_wakeup_isr(void)
{
@@ -720,13 +670,6 @@ static void handle_d0i3(void)
aon_share.pg_exit = 0;
}
-#if defined(CHIP_VARIANT_ISH5P4)
- /* Set PMC LTR to 2ms before DMA copy */
- if (IS_ENABLED(CONFIG_ISH_NEW_PM))
- sb_upstream_write_raw(0, LTR_CMD_ATTR, LTR_CMD_DATA_2MS,
- SBEP_PMC_SAIRS_VAL);
-#endif
-
/* store main FW 's context to IMR DDR from main SRAM */
ret = store_main_fw();
@@ -737,13 +680,6 @@ static void handle_d0i3(void)
/* power off main SRAM */
sram_power(0);
-#if defined(CHIP_VARIANT_ISH5P4)
- /* Set LTR to a large number after DMA copy done */
- if (IS_ENABLED(CONFIG_ISH_NEW_PM))
- sb_upstream_write_raw(0, LTR_CMD_ATTR, LTR_CMD_DATA_INFINITE,
- SBEP_PMC_SAIRS_VAL);
-#endif
-
set_vnnred_aoncg();
if (IS_ENABLED(CONFIG_ISH_IPAPG) && is_ipapg_allowed()) {
@@ -776,13 +712,6 @@ static void handle_d0i3(void)
aon_share.uma_msb);
}
-#if defined(CHIP_VARIANT_ISH5P4)
- /* Set PMC LTR to 2ms before DMA copy */
- if (IS_ENABLED(CONFIG_ISH_NEW_PM))
- sb_upstream_write_raw(0, LTR_CMD_ATTR, LTR_CMD_DATA_2MS,
- SBEP_PMC_SAIRS_VAL);
-#endif
-
/* restore main FW 's context to main SRAM from IMR DDR */
ret = restore_main_fw();
diff --git a/chip/ish/clock.c b/chip/ish/clock.c
index f9fec0b7d2..e46c4278b7 100644
--- a/chip/ish/clock.c
+++ b/chip/ish/clock.c
@@ -7,8 +7,8 @@
#include "clock.h"
#include "common.h"
-#include "power_mgt.h"
#include "util.h"
+#include "power_mgt.h"
/* Console output macros */
#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
diff --git a/chip/ish/dma.c b/chip/ish/dma.c
index eae6a850f1..48a27a0463 100644
--- a/chip/ish/dma.c
+++ b/chip/ish/dma.c
@@ -7,12 +7,34 @@
#include "common.h"
#include "console.h"
-#include "ish_dma.h"
#include "registers.h"
+#include "ish_dma.h"
#include "util.h"
static int dma_init_called; /* If ish_dma_init is called */
+static int dma_poll(uint32_t addr, uint32_t expected, uint32_t mask)
+{
+ int retval = -1;
+ uint32_t counter = 0;
+
+ /*
+ * The timeout is approximately 2.2 seconds according to
+ * value of UINT32_MAX, 120MHZ ISH clock frequency and
+ * instruction count which is around 4.
+ */
+ while (counter < (UINT32_MAX / 64)) {
+ /* test condition */
+ if ((REG32(addr) & mask) == expected) {
+ retval = DMA_RC_OK;
+ break;
+ }
+ counter++;
+ }
+
+ return retval;
+}
+
void ish_dma_ocp_timeout_disable(void)
{
if (!IS_ENABLED(CONFIG_ISH_NEW_PM)) {
@@ -22,6 +44,24 @@ void ish_dma_ocp_timeout_disable(void)
}
}
+static inline uint32_t interrupt_lock(void)
+{
+ uint32_t eflags = 0;
+ __asm__ volatile("pushfl;" /* save eflag value */
+ "popl %0;"
+ "cli;"
+ : "=r"(eflags)); /* shut off interrupts */
+ return eflags;
+}
+
+static inline void interrupt_unlock(uint32_t eflags)
+{
+ __asm__ volatile("pushl %0;" /* restore elfag values */
+ "popfl;"
+ :
+ : "r"(eflags));
+}
+
void dma_configure_psize(void)
{
/* Give chan0 512 bytes for high performance, and chan1 128 bytes. */
diff --git a/chip/ish/hbm.h b/chip/ish/hbm.h
index 17c7853b1d..d666f748c8 100644
--- a/chip/ish/hbm.h
+++ b/chip/ish/hbm.h
@@ -6,10 +6,10 @@
#ifndef __HBM_H
#define __HBM_H
-#include "heci_client.h"
-
-#include <stddef.h>
#include <stdint.h>
+#include <stddef.h>
+
+#include "heci_client.h"
#define HBM_MAJOR_VERSION 1
#ifdef HECI_ENABLE_DMA
diff --git a/chip/ish/heci_client.h b/chip/ish/heci_client.h
index 2ba9ea01db..951b82c6d9 100644
--- a/chip/ish/heci_client.h
+++ b/chip/ish/heci_client.h
@@ -6,10 +6,10 @@
#ifndef __HECI_CLIENT_H
#define __HECI_CLIENT_H
-#include "hooks.h"
-
-#include <stddef.h>
#include <stdint.h>
+#include <stddef.h>
+
+#include "hooks.h"
#define HECI_MAX_NUM_OF_CLIENTS 2
diff --git a/chip/ish/hid_device.h b/chip/ish/hid_device.h
index 07d8a77673..ba7722f5bb 100644
--- a/chip/ish/hid_device.h
+++ b/chip/ish/hid_device.h
@@ -6,10 +6,10 @@
#ifndef __HID_DEVICE_H
#define __HID_DEVICE_H
-#include "hooks.h"
-
-#include <stddef.h>
#include <stdint.h>
+#include <stddef.h>
+
+#include "hooks.h"
#define HID_SUBSYS_MAX_PAYLOAD_SIZE 4954
diff --git a/chip/ish/hwtimer.c b/chip/ish/hwtimer.c
index 40c3de67a8..57049a63b3 100644
--- a/chip/ish/hwtimer.c
+++ b/chip/ish/hwtimer.c
@@ -8,9 +8,9 @@
#include "console.h"
#include "hpet.h"
#include "hwtimer.h"
+#include "timer.h"
#include "registers.h"
#include "task.h"
-#include "timer.h"
#include "util.h"
#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
diff --git a/chip/ish/i2c.c b/chip/ish/i2c.c
index 230f073369..e26bcd70e5 100644
--- a/chip/ish/i2c.c
+++ b/chip/ish/i2c.c
@@ -6,16 +6,16 @@
/* I2C port module for ISH */
#include "common.h"
-#include "config_chip.h"
#include "console.h"
+#include "config_chip.h"
#include "gpio.h"
#include "hooks.h"
-#include "hwtimer.h"
#include "i2c.h"
-#include "ish_i2c.h"
#include "registers.h"
+#include "ish_i2c.h"
#include "task.h"
#include "timer.h"
+#include "hwtimer.h"
#include "util.h"
#define CPUTS(outstr) cputs(CC_I2C, outstr)
diff --git a/chip/ish/ipc_heci.c b/chip/ish/ipc_heci.c
index 8ce0a258e1..1fd81e3d3f 100644
--- a/chip/ish/ipc_heci.c
+++ b/chip/ish/ipc_heci.c
@@ -24,15 +24,15 @@
*/
#include "builtin/assert.h"
+#include "registers.h"
#include "console.h"
-#include "hooks.h"
-#include "hwtimer.h"
+#include "task.h"
+#include "util.h"
#include "ipc_heci.h"
#include "ish_fwst.h"
#include "queue.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
+#include "hooks.h"
+#include "hwtimer.h"
#define CPUTS(outstr) cputs(CC_LPC, outstr)
#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
diff --git a/chip/ish/ipc_heci.h b/chip/ish/ipc_heci.h
index 96b08f9c4a..f9372aefa3 100644
--- a/chip/ish/ipc_heci.h
+++ b/chip/ish/ipc_heci.h
@@ -7,8 +7,6 @@
#ifndef __IPC_HECI_H
#define __IPC_HECI_H
-#include <stddef.h>
-
enum IPC_ERR {
IPC_ERR_IPC_IS_NOT_READY = EC_ERROR_INTERNAL_FIRST + 0,
IPC_ERR_TOO_SMALL_BUFFER = EC_ERROR_INTERNAL_FIRST + 1,
diff --git a/chip/ish/ish_dma.h b/chip/ish/ish_dma.h
index 89d6cb7342..fb9c4f4f06 100644
--- a/chip/ish/ish_dma.h
+++ b/chip/ish/ish_dma.h
@@ -27,47 +27,6 @@
#define PAGE_SIZE 4096
-static inline uint32_t interrupt_lock(void)
-{
- uint32_t eflags = 0;
-
- __asm__ volatile("pushfl;" /* save eflag value */
- "popl %0;"
- "cli;"
- : "=r"(eflags)); /* shut off interrupts */
- return eflags;
-}
-
-static inline void interrupt_unlock(uint32_t eflags)
-{
- __asm__ volatile("pushl %0;" /* restore elfag values */
- "popfl;"
- :
- : "r"(eflags));
-}
-
-static inline int dma_poll(uint32_t addr, uint32_t expected, uint32_t mask)
-{
- int retval = -1;
- uint32_t counter = 0;
-
- /*
- * The timeout is approximately 2.2 seconds according to
- * value of UINT32_MAX, 120MHZ ISH clock frequency and
- * instruction count which is around 4.
- */
- while (counter < (UINT32_MAX / 64)) {
- /* test condition */
- if ((REG32(addr) & mask) == expected) {
- retval = DMA_RC_OK;
- break;
- }
- counter++;
- }
-
- return retval;
-}
-
/**
* SRAM: ISH local static ram
* UMA: Protected system DRAM region dedicated for ISH
diff --git a/chip/ish/ish_i2c.h b/chip/ish/ish_i2c.h
index 7aa2977178..c24f4e0cdc 100644
--- a/chip/ish/ish_i2c.h
+++ b/chip/ish/ish_i2c.h
@@ -6,9 +6,8 @@
#ifndef __CROS_EC_ISH_I2C_H
#define __CROS_EC_ISH_I2C_H
-#include "task.h"
-
#include <stdint.h>
+#include "task.h"
#define I2C_TSC_TIMEOUT 2000000
#define I2C_CALIB_ADDRESS 0x3
diff --git a/chip/ish/ish_persistent_data.c b/chip/ish/ish_persistent_data.c
index ed909d6f7b..149acaeade 100644
--- a/chip/ish/ish_persistent_data.c
+++ b/chip/ish/ish_persistent_data.c
@@ -4,11 +4,11 @@
*/
#include "common.h"
-#include "config.h"
#include "ec_commands.h"
+#include "config.h"
#include "hooks.h"
-#include "ish_persistent_data.h"
#include "system.h"
+#include "ish_persistent_data.h"
#define PERSISTENT_DATA_MAGIC 0x49534864 /* "ISHd" */
diff --git a/chip/ish/power_mgt.c b/chip/ish/power_mgt.c
index de9022b55a..83ef0fc91b 100644
--- a/chip/ish/power_mgt.c
+++ b/chip/ish/power_mgt.c
@@ -3,6 +3,8 @@
* found in the LICENSE file.
*/
+#include <stdnoreturn.h>
+
#include "aontaskfw/ish_aon_share.h"
#include "console.h"
#include "hwtimer.h"
@@ -15,8 +17,6 @@
#include "util.h"
#include "watchdog.h"
-#include <stdnoreturn.h>
-
#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
@@ -612,18 +612,8 @@ void ish_pm_init(void)
/* clear reset history register in CCU */
CCU_RST_HST = CCU_RST_HST;
-#if defined(CHIP_VARIANT_ISH5P4)
- if (IS_ENABLED(CONFIG_ISH_NEW_PM))
- PMU_D3_STATUS_1 = 0xffffffff;
-#endif
-
/* disable TCG and disable BCG */
- CCU_TCG_ENABLE = 0;
- CCU_BCG_ENABLE = 0;
-
- /* Disable power gate of CACHE and ROM */
- PMU_RF_ROM_PWR_CTRL = 0;
-
+ CCU_TCG_EN = 0;
reset_bcg();
if (IS_ENABLED(CONFIG_ISH_PM_AONTASK))
@@ -634,15 +624,8 @@ void ish_pm_init(void)
PMU_GPIO_WAKE_MASK1 = 0;
}
- /* Unmask all wake up events in event1 */
+ /* unmask all wake up events */
PMU_MASK_EVENT = ~PMU_MASK_EVENT_BIT_ALL;
- /* Mask events in event2 */
- PMU_MASK_EVENT2 = PMU_MASK2_ALL_EVENTS;
-
-#if defined(CHIP_VARIANT_ISH5P4)
- SBEP_REG_CLK_GATE_ENABLE =
- (SB_CLK_GATE_EN_LOCAL_CLK_GATE | SB_CLK_GATE_EN_TRUNK_CLK_GATE);
-#endif
if (IS_ENABLED(CONFIG_ISH_NEW_PM)) {
PMU_ISH_FABRIC_CNT = (PMU_ISH_FABRIC_CNT & 0xffff0000) |
@@ -665,15 +648,6 @@ void ish_pm_init(void)
(PMU_D3_STATUS & PMU_BME_BIT_SET))
PMU_D3_STATUS = PMU_D3_STATUS;
-#if defined(CHIP_VARIANT_ISH5P4)
- if (IS_ENABLED(CONFIG_ISH_NEW_PM)) {
- /* Mask all function1 */
- PMU_REG_MASK_D3_RISE = 0x2;
- PMU_REG_MASK_D3_FALL = 0x2;
- PMU_REG_MASK_BME_RISE = 0x2;
- PMU_REG_MASK_BME_FALL = 0x2;
- }
-#endif
enable_d3bme_irqs();
}
}
diff --git a/chip/ish/power_mgt.h b/chip/ish/power_mgt.h
index a7a702018f..851529ffb1 100644
--- a/chip/ish/power_mgt.h
+++ b/chip/ish/power_mgt.h
@@ -6,11 +6,11 @@
#ifndef __CROS_EC_POWER_MGT_H
#define __CROS_EC_POWER_MGT_H
+#include <stdnoreturn.h>
+
#include "common.h"
#include "registers.h"
-#include <stdnoreturn.h>
-
extern void uart_port_restore(void);
extern void uart_to_idle(void);
extern void clear_fabric_error(void);
diff --git a/chip/ish/registers.h b/chip/ish/registers.h
index 7fe5d2c5ab..bdd04a7cb2 100644
--- a/chip/ish/registers.h
+++ b/chip/ish/registers.h
@@ -48,7 +48,6 @@ enum ish_i2c_port {
#define ISH_IOAPIC_BASE 0xFEC00000
#define ISH_HPET_BASE 0x04700000
#define ISH_LAPIC_BASE 0xFEE00000
-#define ISH_SBEP_BASE 0x04500000
#else
#define ISH_I2C0_BASE 0x00100000
#define ISH_I2C1_BASE 0x00102000
@@ -129,66 +128,6 @@ enum ish_i2c_port {
#define ISH_GPIO_GWSR REG32(ISH_GPIO_BASE + 0x118) /* Wake Source */
#define ISH_GPIO_GSEC REG32(ISH_GPIO_BASE + 0x130) /* Secure Input */
-#if defined(CHIP_VARIANT_ISH5P4)
-/* Side Band End Point registers */
-#define SBEP_REG_CLK_GATE_ENABLE REG32(ISH_SBEP_BASE + 0x006C)
-#define SB_CLK_GATE_EN_LOCAL_CLK_GATE BIT(0)
-#define SB_CLK_GATE_EN_TRUNK_CLK_GATE BIT(1)
-#endif
-
-#define SBEP_REG_UP_MSG_STATUS_ADDR (ISH_SBEP_BASE + 0x0040)
-#define SBEP_REG_UP_MSG_STATUS REG32(ISH_SBEP_BASE + 0x0040)
-#define SBEP_REG_UP_MSG_COMMAND REG32(ISH_SBEP_BASE + 0x0044)
-#define SBEP_REG_UP_MSG_REQ_ADDR_LOW REG32(ISH_SBEP_BASE + 0x0048)
-#define SBEP_REG_UP_MSG_REQ_ADDR_HIGH REG32(ISH_SBEP_BASE + 0x004C)
-#define SBEP_REG_UP_MSG_REQ_DATA REG32(ISH_SBEP_BASE + 0x0050)
-#define SBEP_REG_UP_MSG_REQ_ATTR REG32(ISH_SBEP_BASE + 0x0054)
-#define SBEP_REG_UP_MSG_REQ_EH REG32(ISH_SBEP_BASE + 0x0058)
-
-#define UP_STATUS_BUSY_MASK 0x01
-#define UP_STATUS_MSG_SENT_MASK 0x02
-#define UP_STATUS_MSG_SENT_CLR 0x02
-
-#define SBEP_CMD_ACTION 0x1
-#define SBEP_CMD_TYPE_WRITE 0x0
-#define SBEP_CMD_TYPE_READ 0x1
-#define SBEP_CMD_POSTED 0x1
-#define SBEP_CMD_NON_POSTED 0x0
-#define SBEP_CMD_INT_ENABLED 0x1
-#define SBEP_CMD_ACTION_OFF 0
-#define SBEP_CMD_TYPE_OFF 1
-#define SBEP_CMD_POSTED_OFF 2
-#define SBEP_CMD_INT_OFF 3
-
-#define SBEP_CMD_WRITE \
- ((SBEP_CMD_ACTION << SBEP_CMD_ACTION_OFF) | \
- (SBEP_CMD_TYPE_WRITE << SBEP_CMD_TYPE_OFF) | \
- (SBEP_CMD_POSTED << SBEP_CMD_POSTED_OFF) | \
- (SBEP_CMD_INT_ENABLED << SBEP_CMD_INT_OFF))
-
-#define SBEP_ATTR_LTR_OPCODE 0x43
-#define SBEP_ATTR_PMC_DEST_ID 0xCC
-#define SBEP_ATTR_DEST_ID_OFF 0
-#define SBEP_ATTR_OPCODE_OFF 8
-#define SBEP_ATTR_WRITE_ALL_BYTES 0xF
-#define SBEP_ATTR_BYTE_ENABLE_OFF 16
-#define LTR_CMD_ATTR \
- ((SBEP_ATTR_PMC_DEST_ID << SBEP_ATTR_DEST_ID_OFF) | \
- (SBEP_ATTR_LTR_OPCODE << SBEP_ATTR_OPCODE_OFF) | \
- (SBEP_ATTR_WRITE_ALL_BYTES << SBEP_ATTR_BYTE_ENABLE_OFF))
-#define LTR_CMD_DATA_2MS 0x90029002
-#define LTR_CMD_DATA_INFINITE 0
-
-#define SBEP_SAIRS_ROOT_SPACE_PMC 0
-
-#define SBEP_SAIRS_EH_PRESENT 1
-#define SBEP_SAIRS_ROOT_SPACE_OFF 16
-#define SBEP_SAIRS_EH_PRESENT_OFF 31
-
-#define SBEP_PMC_SAIRS_VAL \
- ((SBEP_SAIRS_ROOT_SPACE_PMC << SBEP_SAIRS_ROOT_SPACE_OFF) | \
- (SBEP_SAIRS_EH_PRESENT << SBEP_SAIRS_EH_PRESENT_OFF))
-
/* APIC interrupt vectors */
#define ISH_TS_VECTOR 0x20 /* Task switch vector */
#define LAPIC_LVT_ERROR_VECTOR 0x21 /* Clears IOAPIC/LAPIC sync errors */
@@ -269,7 +208,6 @@ enum ish_i2c_port {
#define PMU_PMC_PG_WAKE REG32(ISH_PMU_BASE + 0xF18)
#define PMU_INTERNAL_PCE REG32(ISH_PMU_BASE + 0xF30)
#define PMU_D3_STATUS REG32(ISH_PMU_BASE + 0x100)
-#define PMU_D3_STATUS_1 REG32(ISH_PMU_BASE + 0x104)
#define PMU_HOST_RST_B BIT(0)
#define PMU_PCE_SHADOW_MASK 0x1F
#define PMU_PCE_PG_ALLOWED BIT(4)
@@ -294,10 +232,6 @@ enum ish_i2c_port {
#define PMU_BME_BIT_FALLING_EDGE_STATUS BIT(26)
#define PMU_BME_BIT_RISING_EDGE_MASK BIT(27)
#define PMU_BME_BIT_FALLING_EDGE_MASK BIT(28)
-#define PMU_REG_MASK_D3_RISE REG32(ISH_PMU_BASE + 0x200)
-#define PMU_REG_MASK_D3_FALL REG32(ISH_PMU_BASE + 0x208)
-#define PMU_REG_MASK_BME_RISE REG32(ISH_PMU_BASE + 0x220)
-#define PMU_REG_MASK_BME_FALL REG32(ISH_PMU_BASE + 0x228)
#endif
#define PMU_GPIO_WAKE_MASK0 REG32(ISH_PMU_BASE + 0x250)
@@ -322,7 +256,6 @@ enum ish_i2c_port {
#define VNN_ID_DMA0 4
#define VNN_ID_DMA(chan) (VNN_ID_DMA0 + chan)
-#define VNN_ID_SIDEBAND 21
/* OCP registers */
#define OCP_IOSF2OCP_BRIDGE (ISH_OCP_BASE + 0x9400)
@@ -389,7 +322,6 @@ enum ish_i2c_port {
#define DEST_BURST_SIZE 3
#define PMU_MASK_EVENT REG32(ISH_PMU_BASE + 0x10)
-#define PMU_MASK_EVENT2 REG32(ISH_PMU_BASE + 0x4C)
#define PMU_MASK_EVENT_BIT_GPIO(pin) BIT(pin)
#define PMU_MASK_EVENT_BIT_HPET BIT(16)
#define PMU_MASK_EVENT_BIT_IPC BIT(17)
@@ -400,16 +332,6 @@ enum ish_i2c_port {
#define PMU_MASK_EVENT_BIT_SPI BIT(22)
#define PMU_MASK_EVENT_BIT_UART BIT(23)
#define PMU_MASK_EVENT_BIT_ALL (0xffffffff)
-#define PMU_MASK_EVENT2_SRAM_ERASE1 BIT(3)
-#define PMU_MASK_EVENT2_SRAM_ERASE0 BIT(4)
-#define PMU_MASK_EVENT2_ISOL_ACK_RISE BIT(14)
-#define PMU_MASK_EVENT2_ISOL_ACK_FALL BIT(15)
-#define PMU_MASK_EVENT2_HOST_RST_RISE BIT(16)
-#define PMU_MASK_EVENT2_HOST_RST_FALL BIT(17)
-#define PMU_MASK2_ALL_EVENTS \
- (PMU_MASK_EVENT2_SRAM_ERASE0 | PMU_MASK_EVENT2_SRAM_ERASE1 | \
- PMU_MASK_EVENT2_ISOL_ACK_RISE | PMU_MASK_EVENT2_ISOL_ACK_FALL | \
- PMU_MASK_EVENT2_HOST_RST_RISE | PMU_MASK_EVENT2_HOST_RST_FALL)
#define PMU_RF_ROM_PWR_CTRL REG32(ISH_PMU_BASE + 0x30)
diff --git a/chip/ish/system_state_subsys.c b/chip/ish/system_state_subsys.c
index 76053dcded..bfc120ff9b 100644
--- a/chip/ish/system_state_subsys.c
+++ b/chip/ish/system_state_subsys.c
@@ -3,10 +3,10 @@
* found in the LICENSE file.
*/
-#include "console.h"
#include "heci_client.h"
#include "registers.h"
#include "system_state.h"
+#include "console.h"
#ifdef SS_SUBSYSTEM_DEBUG
#define CPUTS(outstr) cputs(CC_LPC, outstr)
diff --git a/chip/ish/uart.c b/chip/ish/uart.c
index 0ff03da89a..b1c9493869 100644
--- a/chip/ish/uart.c
+++ b/chip/ish/uart.c
@@ -4,16 +4,17 @@
*/
/* UART module for ISH */
-#include "atomic.h"
#include "common.h"
-#include "console.h"
-#include "interrupts.h"
#include "math_util.h"
-#include "registers.h"
-#include "system.h"
+#include "console.h"
+#include "uart_defs.h"
+#include "atomic.h"
#include "task.h"
+#include "registers.h"
#include "uart.h"
#include "uart_defs.h"
+#include "interrupts.h"
+#include "system.h"
#define CPUTS(outstr) cputs(CC_LPC, outstr)
#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
diff --git a/chip/ish/uart_defs.h b/chip/ish/uart_defs.h
index 581a702d31..1fc36b7adc 100644
--- a/chip/ish/uart_defs.h
+++ b/chip/ish/uart_defs.h
@@ -8,10 +8,9 @@
#ifndef __CROS_EC_UART_DEFS_H_
#define __CROS_EC_UART_DEFS_H_
-#include "atomic.h"
-
-#include <stddef.h>
#include <stdint.h>
+#include <stddef.h>
+#include "atomic.h"
#define UART_ERROR -1
#define UART_BUSY -2
diff --git a/chip/ish/watchdog.c b/chip/ish/watchdog.c
index 8f0ea5ddf1..7b32133619 100644
--- a/chip/ish/watchdog.c
+++ b/chip/ish/watchdog.c
@@ -23,9 +23,9 @@
#include "ec_commands.h"
#include "hooks.h"
#include "ish_persistent_data.h"
+#include "task.h"
#include "registers.h"
#include "system.h"
-#include "task.h"
#include "watchdog.h"
/* Units are hundreds of milliseconds */
View Lorry Controller Status