malefor: Initial EC imagestabilize-12951.B-master

Create the initial EC image for the malefor variant of the
volteer baseboard by copying the baseboard EC files into a new
directory named for the variant.

(Auto-Generated by create_initial_ec_image.sh version 1.0.1).

BUG=b:150653745
BRANCH=none
TEST=make BOARD=malefor

Signed-off-by: xiong.huang <xiong.huang@bitland.corp-partner.google.com>
Change-Id: I58c679fb1150997c199dda23fd69d23480a0fb80
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2082304
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>

7 files changed, 645 insertions, 0 deletions

diff --git a/board/malefor/battery.c b/board/malefor/battery.c
new file mode 100644
index 0000000000..9b356a8efd
--- /dev/null
+++ b/board/malefor/battery.c
@@ -0,0 +1,68 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "util.h"
+
+/*
+ * Battery info for all Volteer battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* LGC\011 L17L3PB0 Battery Information */
+	/*
+	 * Battery info provided by ODM on b/143477210, comment #11
+	 */
+	[BATTERY_LGC011] = {
+		.fuel_gauge = {
+			.manuf_name = "LGC",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x10, 0x10 },
+			},
+			.fet = {
+				.reg_addr = 0x0,
+				.reg_mask = 0x6000,
+				.disconnect_val = 0x6000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
+			.voltage_normal		= 11550, /* mV */
+			.voltage_min		= 9000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 45,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= 0,
+			.discharging_max_c	= 75,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC011;
diff --git a/board/malefor/board.c b/board/malefor/board.c
new file mode 100644
index 0000000000..c0466dec76
--- /dev/null
+++ b/board/malefor/board.c
@@ -0,0 +1,60 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Volteer board-specific configuration */
+
+#include "button.h"
+#include "common.h"
+#include "accelgyro.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/als_tcs3400.h"
+#include "driver/sync.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "switch.h"
+#include "system.h"
+#include "task.h"
+#include "tablet_mode.h"
+#include "uart.h"
+#include "usb_pd_tbt.h"
+#include "util.h"
+
+#include "gpio_list.h" /* Must come after other header files. */
+
+static void board_init(void)
+{
+	/* TODO */
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
+{
+	/* Routing length exceeds 205mm prior to connection to re-timer */
+	if (port == USBC_PORT_C1)
+		return TBT_SS_U32_GEN1_GEN2;
+
+	/*
+	 * Thunderbolt-compatible mode not supported
+	 *
+	 * TODO (b/147726366): All the USB-C ports need to support same speed.
+	 * Need to fix once USB-C feature set is known for Volteer.
+	 */
+	return TBT_SS_RES_0;
+}
+
+__override bool board_is_tbt_usb4_port(int port)
+{
+	/*
+	 * On Proto-1 only Port 1 supports TBT & USB4
+	 *
+	 * TODO (b/147732807): All the USB-C ports need to support same
+	 * features. Need to fix once USB-C feature set is known for Volteer.
+	 */
+	return port == USBC_PORT_C1;
+}
diff --git a/board/malefor/board.h b/board/malefor/board.h
new file mode 100644
index 0000000000..1a9d2bf271
--- /dev/null
+++ b/board/malefor/board.h
@@ -0,0 +1,91 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Volteer board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/* Optional features */
+#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
+
+#define CONFIG_POWER_BUTTON
+
+#undef CONFIG_UART_TX_BUF_SIZE
+#define CONFIG_UART_TX_BUF_SIZE 4096
+
+/* Keyboard features */
+
+/* Sensors */
+
+/* USB Type C and USB PD defines */
+/*
+ * USB-C port's USB2 & USB3 mapping from schematics
+ * USB2 numbering on PCH - 1 to n
+ * USB3 numbering on AP - 0 to n (PMC's USB3 numbering for MUX
+ * configuration is - 1 to n hence add +1)
+ */
+#define USBC_PORT_0_USB2_NUM	9
+#define USBC_PORT_0_USB3_NUM	1
+#define USBC_PORT_1_USB2_NUM	4
+#define USBC_PORT_1_USB3_NUM	2
+
+/* USB Type A Features */
+
+/* BC 1.2 */
+
+/* Volume Button feature */
+
+/* Fan features */
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT			GPIO_ACOK_OD
+#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
+#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SYS_PWROK		GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
+#define GPIO_PG_EC_DSW_PWROK		GPIO_DSW_PWROK
+#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
+#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
+#define GPIO_WP_L			GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
+#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
+#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum battery_type {
+	BATTERY_LGC011,
+	BATTERY_TYPE_COUNT,
+};
+
+/* TODO: b/143375057 - Remove this code after power on. */
+void c10_gate_change(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/malefor/build.mk b/board/malefor/build.mk
new file mode 100644
index 0000000000..5a2ccd3d79
--- /dev/null
+++ b/board/malefor/build.mk
@@ -0,0 +1,32 @@
+# -*- makefile -*-
+# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m6fc
+BASEBOARD:=volteer
+
+# TODO: b/143375057 - Remove this code after power on.
+#
+# Temporary for board power on.  Provide a Volteer specific make option
+# to enable the power signal GPIOs that are not stuffed by default.  This
+# is a backup if board logic power sequencing needs to be adjusted.
+#
+# Set the following variable to 'y' to enable the Volteer optional power signals
+VOLTEER_POWER_SEQUENCE=
+ifneq (,$(VOLTEER_POWER_SEQUENCE))
+CFLAGS_BASEBOARD+=-DVOLTEER_POWER_SEQUENCE
+endif
+
+# Force changes to VOLTEER_POWER_SEQUENCE variable to trigger a full build.
+ENV_VARS := VOLTEER_POWER_SEQUENCE
+
+
+board-y=board.o
+board-y+=battery.o
+board-$(VOLTEER_POWER_SEQUENCE)+=power_sequence.o
diff --git a/board/malefor/ec.tasklist b/board/malefor/ec.tasklist
new file mode 100644
index 0000000000..99ed79f1c8
--- /dev/null
+++ b/board/malefor/ec.tasklist
@@ -0,0 +1,26 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(PDCMD, pd_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/malefor/gpio.inc b/board/malefor/gpio.inc
new file mode 100644
index 0000000000..93f48572e1
--- /dev/null
+++ b/board/malefor/gpio.inc
@@ -0,0 +1,185 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Wake Source interrupts */
+GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
+GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
+GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
+
+/* Optional power sequencing interrupts */
+#ifdef VOLTEER_POWER_SEQUENCE
+GPIO_INT(CPU_C10_GATE_L,       PIN(6, 7), GPIO_INT_BOTH, c10_gate_change)
+#endif
+
+/* Power sequencing interrupts */
+GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+#endif
+GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(DSW_PWROK,            PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4),  GPIO_INT_BOTH, power_signal_interrupt)
+
+/* Sensor Interrupts */
+GPIO_INT(EC_CAM_VSYN_SLP_S0IX, PIN(7, 2), GPIO_INT_RISING, sync_interrupt)
+GPIO_INT(EC_ALS_RGB_INT_L,     PIN(D, 4), GPIO_INT_FALLING, tcs3400_interrupt)
+GPIO_INT(TABLET_MODE_L,        PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+
+/* USB-C interrupts */
+GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
+GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
+
+GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
+
+GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
+GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
+
+/* HDMI interrupts */
+
+/* Volume button interrupts */
+GPIO_INT(EC_VOLDN_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+/*
+ * EC_VOLUP_BTN_ODL moved from GPIO75 to GPIO97 on boards with board ID >=1.
+ * GPIO97/EN_PP1050_BYPASS is DNS on board ID 0, and GPIO75 will be used once
+ * EFS support is added.
+ * TODO (b/149858568): remove board ID=0 support.
+ */
+GPIO_INT(EC_VOLUP_BTN_ODL_BOARDID_0,	PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_VOLUP_BTN_ODL,		PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+
+/* Power Sequencing Signals */
+GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
+GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
+/* The EC does not buffer this signal on Volteer. */
+UNIMPLEMENTED(PCH_DSW_PWROK)
+
+#ifdef VOLTEER_POWER_SEQUENCE
+/* Optional power sequencing signals that are not stuffed by default */
+GPIO(EN_DRAM_VDDQ,		PIN(F, 2), GPIO_OUT_LOW)
+GPIO(EN_PP1050_STG,		PIN(C, 0), GPIO_OUT_LOW)
+GPIO(EN_PP5000_USB_AG,		PIN(A, 7), GPIO_OUT_LOW)
+GPIO(EN_PPVAR_VCCIN_AUX,	PIN(8, 1), GPIO_OUT_LOW)
+GPIO(EN_PP1050_ST_S0,		PIN(3, 4), GPIO_OUT_LOW)
+GPIO(EN_VNN_BYPASS,		PIN(B, 0), GPIO_OUT_LOW)
+GPIO(EN_DRAM_VDD1,		PIN(9, 6), GPIO_OUT_LOW)
+#endif
+
+/* Other wake sources */
+/*
+ * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
+ * interrupt handler because it is automatically handled by the PSL.
+ *
+ * We need to lock the setting so this gpio can't be reconfigured to overdrive
+ * the real reset signal. (This is the PSL input pin not the real reset pin).
+ */
+GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
+					   GPIO_HIB_WAKE_HIGH |
+					   GPIO_LOCKED)
+
+/* AP/PCH Signals */
+GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
+GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
+GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
+GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
+
+GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
+
+/* USB and USBC Signals */
+
+/*
+ * USB_C1 moved from GPIO32 to GPIO83 on boards with board ID >=1.
+ * GPIO83/EN_PP1800_A is DNS on board ID 0 and GPIO32 is N/C on board ID >=1
+ * so it's safe to define GPIOs compatible with both designs.
+ * TODO (b/149858568): remove board ID=0 support.
+ */
+GPIO(USB_C1_RT_RST_ODL_BOARDID_0,	PIN(3, 2), GPIO_ODR_LOW) /* USB_C1 Reset on boards without board ID */
+GPIO(USB_C1_RT_RST_ODL,			PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset on boards board ID >=1 */
+
+/* Don't have a load switch for retimer */
+UNIMPLEMENTED(USB_C1_LS_EN)
+/* Retimer Force Power enable is connected to AP */
+UNIMPLEMENTED(USB_C1_RT_FORCE_PWR)
+
+/* Misc Signals */
+
+/*
+ * eDP backlight - both PCH and EC have enable pins that must be high
+ * for the backlight to turn on. Default state is high, and can be turned
+ * off during sleep states.
+ */
+GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
+
+/* I2C pins - Alternate function below configures I2C module on these pins */
+GPIO(EC_I2C0_SENSOR_SCL,       PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C0_SENSOR_SDA,       PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C3_USB_1_MIX_SCL,    PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C3_USB_1_MIX_SDA,    PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C5_POWER_SCL,        PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C5_POWER_SDA,        PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C7_EEPROM_SCL,       PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C7_EEPROM_SDA,       PIN(B, 2), GPIO_INPUT)
+
+/* Battery signals */
+GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
+
+/* Physical HPD pins are not needed on EC as these are configured by PMC */
+GPIO(USB_C0_DP_HPD,		PIN(F, 3), GPIO_INPUT)
+GPIO(USB_C1_DP_HPD,		PIN(7, 0), GPIO_INPUT)
+
+/* Alternate functions GPIO definitions */
+ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* I2C0 */
+ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
+ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
+ALTERNATE(PIN_MASK(D, BIT(1) | BIT(0)), 0, MODULE_I2C, 0)                            /* I2C3 */
+ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
+ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
+
+/* This selects between an LED module on the motherboard and one on the daughter
+ * board, to be controlled by LED_{1,2,3}_L. PWM allows driving both modules at
+ * the same time. */
+ALTERNATE(PIN_MASK(6, BIT(0)), 0, MODULE_PWM, 0)                                     /* LED_SIDESEL_4_L */
+ALTERNATE(PIN_MASK(C, BIT(2) | BIT(3) | BIT(4)), 0, MODULE_PWM, 0)                   /* LED_{3,2,1}_L */
+
+/* Fan signals */
+GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
+ALTERNATE(PIN_MASK(B, BIT(7)), 0, MODULE_PWM, 0)	/* FAN_PWM */
+ALTERNATE(PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0)	/* FAN_SPEED_TACH */
+
+/* Keyboard pins */
+#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
+ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
+GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
+ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
+ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
+ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
+ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
+
+/* UART */
+ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
+
+/* Power Switch Logic (PSL) inputs */
+ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
+ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
+                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
+                                                                       GPIO02 = EC_RST_ODL */
+
diff --git a/board/malefor/power_sequence.c b/board/malefor/power_sequence.c
new file mode 100644
index 0000000000..ac244c179d
--- /dev/null
+++ b/board/malefor/power_sequence.c
@@ -0,0 +1,183 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Volteer board-specific power sequencing
+ * Power sequencing is largely done by the platform automatically.
+ * However, if platform power sequencing is buggy or needs tuning,
+ * resistors can be stuffed on the board to allow the EC full control over
+ * the power sequencing.
+ */
+
+#include "assert.h"
+#include "chipset.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "system.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define GPIO_SET_VERBOSE(signal, value) \
+	gpio_set_level_verbose(CC_CHIPSET, signal, value)
+
+static void board_wakeup(void)
+{
+	CPRINTS("%s", __func__);
+	/*
+	 * PP5000_USB_AG - normally enabled automatically by EN_3300_AG which
+	 * is connected to the PSL_OUT of the Nuvoton.
+	 *
+	 * Assert the signal high during wakeup, deassert at hibernate
+	 */
+	GPIO_SET_VERBOSE(GPIO_EN_PP5000_USB_AG, 1);
+}
+DECLARE_HOOK(HOOK_INIT, board_wakeup, HOOK_PRIO_DEFAULT);
+
+__override void board_hibernate_late(void)
+{
+	CPRINTS("%s", __func__);
+	/* Disable PP5000_USB_AG on hibernate */
+	GPIO_SET_VERBOSE(GPIO_EN_PP5000_USB_AG, 0);
+}
+
+/* Called during S5 -> S3 transition */
+static void board_chipset_startup(void)
+{
+	CPRINTS("%s", __func__);
+
+	/*
+	 *
+	 */
+
+	/*
+	 * Power on 1.8V rail,
+	 * tPCH06, minimum 200us from P-P3300_DSW stable to before
+	 * VCCPRIM_1P8 starting up.
+	 *
+	 * The transition to S5 and S3 is gated by SLP_SUS#, which Tiger Lake
+	 * internally delays a minimum of 95 ms from DSW_PWROK. So no delay
+	 * needed here.
+	 */
+	GPIO_SET_VERBOSE(GPIO_EN_PP1800_A, 1);
+
+	/*
+	 * Power on VCCIN Aux - no delay specified, but must follow VCCPRIM_1P8
+	 */
+	GPIO_SET_VERBOSE(GPIO_EN_PPVAR_VCCIN_AUX, 1);
+
+	/*
+	 * Power on bypass rails - must be turned on after VCCIN aux
+	 *
+	 * tPCH34, maximum 50 ms from SLP_SUS# de-assertion to completion of
+	 * primary and bypass rail, no minimum specified.
+	 */
+	GPIO_SET_VERBOSE(GPIO_EN_VNN_BYPASS, 1);
+	GPIO_SET_VERBOSE(GPIO_EN_PP1050_BYPASS, 1);
+
+	/*
+	 * Power on VCCST - must be gated by SLP_S3#.  No order with respect to
+	 * other power signals specified.
+	 */
+	GPIO_SET_VERBOSE(GPIO_EN_PP1050_ST_S0, 1);
+
+	/*
+	 * Power on DDR rails
+	 * No delay needed - SLP_S4# already guaranteed to be de-asserted.
+	 * VDDQ must ramp after VPP (VDD1) for DDR4/LPDDR4 systems.
+	 */
+	GPIO_SET_VERBOSE(GPIO_EN_DRAM_VDD1, 1);
+	GPIO_SET_VERBOSE(GPIO_EN_DRAM_VDDQ, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
+
+/* Called during S3 -> S0 and S0ix -> S0 transition */
+static void board_chipset_resume(void)
+{
+	CPRINTS("%s", __func__);
+	/*
+	 * Power on VCCSTG rail to Tiger Lake, no PG signal available
+	 */
+	GPIO_SET_VERBOSE(GPIO_EN_PP1050_STG, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+
+/* Called during S0 -> S0ix transition */
+static void board_chipset_suspend(void)
+{
+	CPRINTS("%s", __func__);
+	/* Power down VCCSTG rail */
+	GPIO_SET_VERBOSE(GPIO_EN_PP1050_STG, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+/* Called during S3 -> S5 transition */
+static void board_chipset_shutdown(void)
+{
+	CPRINTS("%s", __func__);
+
+	/*
+	 * S0 to G3 sequence 1 of 2 (shared between Deep Sx and non-Deep Sx)
+	 *  TigerLake Rail    Net Name
+	 *  VCCSTG            PP1050_STG_S0
+	 *  DDR_VDDQ          PP0600_VDDQ
+	 *  VCCST             PP1050_ST_S0
+	 *  DDR_VPP           PP1800_DRAM
+	 */
+	GPIO_SET_VERBOSE(GPIO_EN_PP1050_STG, 0);
+	GPIO_SET_VERBOSE(GPIO_EN_DRAM_VDDQ, 0);
+	GPIO_SET_VERBOSE(GPIO_EN_PP1050_ST_S0, 0);
+	GPIO_SET_VERBOSE(GPIO_EN_DRAM_VDD1, 0);
+
+	/*
+	 * S0 to G3 sequence 2 of 2 (non-Deep Sx)
+	 *  TigerLake Name    Net Name
+	 *  VCCPRIM_3P3       PP3300_A
+	 *  VCCDSW_3P3        VCCDSW_3P3 (PP3300_A)
+	 *  V5.0A             PP5000_A
+	 *  VCCPRIM_1P8       PP1800_A
+	 *  VCCIN_AUX         PPVAR_VCCIN_AUX
+	 *  VNN_BYPASS        PPVAR_VNN_BYPASS
+	 *  V1.05A_BYPASS     PP1050_A_BYPASS
+	 */
+
+	/* Ice Lake shutdown already sequences first 3 rails above. */
+	chipset_force_shutdown(CHIPSET_SHUTDOWN_G3);
+
+	GPIO_SET_VERBOSE(GPIO_EN_PP1800_A, 0);
+	GPIO_SET_VERBOSE(GPIO_EN_PPVAR_VCCIN_AUX, 0);
+	GPIO_SET_VERBOSE(GPIO_EN_VNN_BYPASS, 0);
+	GPIO_SET_VERBOSE(GPIO_EN_PP1050_BYPASS, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
+
+/**
+ * Handle C10_GATE transitions - see VCCSTG enable logic (figure 232, page 406)
+ * in Tiger Lake PDG, revision 1.0.
+ *
+ * TODO: b/141322107 - This function can be promoted to common TigerLake power
+ * file if CPU_C10_GATE_L support provided by the platform is not sufficient.
+ */
+void c10_gate_change(enum gpio_signal signal)
+{
+	/* Pass through CPU_C10_GATE_L as enable for VCCSTG rail */
+	int c10_gate_in;
+	int vccstg_out;
+
+	ASSERT(signal == GPIO_CPU_C10_GATE_L);
+
+	c10_gate_in = gpio_get_level(signal);
+	vccstg_out = gpio_get_level(GPIO_EN_PP1050_STG);
+
+	if (vccstg_out == c10_gate_in)
+		return;
+
+	gpio_set_level(GPIO_EN_PP1050_STG, c10_gate_in);
+}
+
+
+
+
+