summaryrefslogtreecommitdiff
path: root/plat/socionext/synquacer
Commit message (Collapse)AuthorAgeFilesLines
* refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3Arvind Ram Prakash2023-03-151-2/+2
| | | | | | | | | | | | | | | | | | | BL2_AT_EL3 is an overloaded macro which has two uses: 1. When BL2 is entry point into TF-A(no BL1) 2. When BL2 is running at EL3 exception level These two scenarios are not exactly same even though first implicitly means second to be true. To distinguish between these two use cases we introduce new macros. BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2. Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where BL2 runs at EL3 (including four world systems). BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the repository. Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72 Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
* build: always prefix section names with `.`Chris Kay2023-02-202-4/+4
| | | | | | | | | | | | | | | | | Some of our specialized sections are not prefixed with the conventional period. The compiler uses input section names to derive certain other section names (e.g. `.rela.text`, `.relacpu_ops`), and these can be difficult to select in linker scripts when there is a lack of a delimiter. This change introduces the period prefix to all specialized section names. BREAKING-CHANGE: All input and output linker section names have been prefixed with the period character, e.g. `cpu_ops` -> `.cpu_ops`. Change-Id: I51c13c5266d5975fbd944ef4961328e72f82fc1c Signed-off-by: Chris Kay <chris.kay@arm.com>
* fix(synquacer): increase size of BL33Jassi Brar2022-09-211-1/+1
| | | | | | | | Increase the max possible size of BL33 from 1MB to 2MB. For example, edk2 is usually bigger than 1MB Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Change-Id: Idd4762e25e623de145c65f31cf2dfe1fee466a74
* fix: make TF-A use provided OpenSSL binarySalome Thirot2022-08-041-3/+3
| | | | | | | | | | | | | Currently Tf-A uses whatever openssl binary is on the system to sign images. However if OPENSSL_DIR is specified in the build flags this can lead to linking issues as the system binary can end up being linked against shared libraries provided in OPENSSL_DIR/lib if both binaries (the system's and the on in OPENSSL_DIR/bin) are the same version. This patch ensures that the binary used is always the one given by OPENSSL_DIR to avoid those link issues. Signed-off-by: Salome Thirot <salome.thirot@arm.com> Change-Id: Ib534e06ebc8482e4391e376d3791a87968de4a99
* feat(synquacer): add FWU Multi Bank Update supportJassi Brar2022-06-272-1/+32
| | | | | | | | | | | | | | Add FWU Multi Bank Update support. This reads the platform metadata and update the FIP base address so that BL2 can load correct BL3X based on the boot index. Cc: Sumit Garg <sumit.garg@linaro.org> Cc: Masahisa Kojima <masahisa.kojima@linaro.org> Cc: Manish V Badarkhe <manish.badarkhe@arm.com> Cc: Leonardo Sandoval <leonardo.sandoval@linaro.org> Change-Id: I5d96972bc4b3b9a12a8157117e53a05da5ce89f6 Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* feat(synquacer): add TBBR supportJassi Brar2022-06-275-0/+166
| | | | | | | | | | | enable Trusted-Boot for Synquacer platform. Cc: Sumit Garg <sumit.garg@linaro.org> Cc: Masahisa Kojima <masahisa.kojima@linaro.org> Cc: Manish V Badarkhe <manish.badarkhe@arm.com> Cc: Leonardo Sandoval <leonardo.sandoval@linaro.org> Change-Id: I2608b4d573d95d55da1fc5544333e0dbf3f763f2 Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* feat(synquacer): add BL2 supportJassi Brar2022-06-279-8/+407
| | | | | | | | | | | | Add BL2 support by default. Move the legacy mode behind the RESET_TO_BL31 define. Cc: Sumit Garg <sumit.garg@linaro.org> Cc: Masahisa Kojima <masahisa.kojima@linaro.org> Cc: Manish V Badarkhe <manish.badarkhe@arm.com> Cc: Leonardo Sandoval <leonardo.sandoval@linaro.org> Change-Id: Ic490745a7e8f6114172733428ebd6bd6adfcc1ec Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* refactor(synquacer): move common source filesJassi Brar2022-06-271-3/+3
| | | | | | | | | | | | Prepare for introduction of BL2 support by moving reusable files from BL31_SOURCES into PLAT_BL_COMMON_SOURCES Cc: Sumit Garg <sumit.garg@linaro.org> Cc: Masahisa Kojima <masahisa.kojima@linaro.org> Cc: Manish V Badarkhe <manish.badarkhe@arm.com> Cc: Leonardo Sandoval <leonardo.sandoval@linaro.org> Change-Id: I21137cdd40d027cfa77f1dec3598ee85d4873581 Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* Merge "fix(plat/socionext/synquacer): initialise CNTFRQ in Non Secure ↵Madhukar Pappireddy2021-12-092-14/+27
|\ | | | | | | CNTBaseN" into integration
| * fix(plat/socionext/synquacer): initialise CNTFRQ in Non Secure CNTBaseNMasahisa Kojima2021-12-072-14/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The GTimer implemented on SynQuacer has similar issue found on Juno wherein CNTBaseN.CNTFRQ can be written but does not reflect the value of the CNTFRQ register in CNTCTLBase frame. This doesn't follow ARM ARM in that the value updated in CNTCTLBase.CNTFRQ is not reflected in CNTBaseN.CNTFRQ. Hence enable the workaround (applied to Juno) for SynQuacer that updates the CNTFRQ register in the Non Secure CNTBaseN frame. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: I5204fb57f28c0945812814f008c4905ef0882e2b
* | refactor(plat/synquacer): update PSCI system_off handlingMasahisa Kojima2021-12-073-0/+10
|/ | | | | | | | | | | | | | | SynQuacer SoC contains a Cortex-M3 System Control Processor(SCP) which manages system power. This commit modifies the PSCI system_off handling to call SCMI, same as other PSCI calls. System power-off is done by turing off the ATX power supply through GPIO, this operation is transferred to SCP. Note that this commit modifies only the SCMI case, obsolete SCPI implementation is not updated. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: I6c1009e67cccd1eb5d14c338c3df9103d63709dd
* fix(plat/synquacer): update scmi power domain off handlingMasahisa Kojima2021-09-141-0/+8
| | | | | | | | | | | | | In the SCMI power domain off handling, configure GIC to prevent interrupt toward to the core to be turned off, and configure CCN to disable coherency when the cluster is turned off. The same operation is done in SCPI power domain off processing. This commit adds the missing operation in SCMI power domain off handling. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: Ib3523de488500c2e8bdc74e4cb8772a1442d9781
* Don't return error information from console_flushJimmy Brisson2020-10-091-3/+3
| | | | | | | | | | | | | And from crash_console_flush. We ignore the error information return by console_flush in _every_ place where we call it, and casting the return type to void does not work around the MISRA violation that this causes. Instead, we collect the error information from the driver (to avoid changing that API), and don't return it to the caller. Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
* xlat_tables_v2: add base table section name parameter for spm_mmMasahisa Kojima2020-06-022-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Core spm_mm code expects the translation tables are located in the inner & outer WBWA & shareable memory. REGISTER_XLAT_CONTEXT2 macro is used to specify the translation table section in spm_mm. In the commit 363830df1c28e (xlat_tables_v2: merge REGISTER_XLAT_CONTEXT_{FULL_SPEC,RO_BASE_TABLE}), REGISTER_XLAT_CONTEXT2 macro explicitly specifies the base xlat table goes into .bss by default. This change affects the existing SynQuacer spm_mm implementation. plat/socionext/synquacer/include/plat.ld.S linker script intends to locate ".bss.sp_base_xlat_table" into "sp_xlat_table" section, but this implementation is no longer available. This patch adds the base table section name parameter for REGISTER_XLAT_CONTEXT2 so that platform can specify the inner & outer WBWA & shareable memory for spm_mm base xlat table. If PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME is not defined, base xlat table goes into .bss by default, the result is same as before. Change-Id: Ie0e1a235e5bd4288dc376f582d6c44c5df6d31b2 Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
* TF-A GICv3 driver: Introduce makefileAlexei Fedorov2020-03-301-5/+4
| | | | | | | | | | | | | | | | | This patch moves all GICv3 driver files into new added 'gicv3.mk' makefile for the benefit of the generic driver which can evolve in the future without affecting platforms. The patch adds GICv3 driver configuration flags 'GICV3_IMPL', 'GICV3_IMPL_GIC600_MULTICHIP' and 'GICV3_OVERRIDE_DISTIF_PWR_OPS' described in 'GICv3 driver options' section of 'build-option.rst' document. NOTE: Platforms with GICv3 driver need to be modified to include 'drivers/arm/gic/v3/gicv3.mk' in their makefiles. Change-Id: If055f6770ff20f5dee5a3c99ae7ced7cdcac5c44 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* TF-A GICv3 driver: Separate GICD and GICR accessor functionsAlexei Fedorov2020-03-101-1/+3
| | | | | | | | | | | | This patch provides separation of GICD, GICR accessor functions and adds new macros for GICv3 registers access as a preparation for GICv3.1 and GICv4 support. NOTE: Platforms need to modify to include both 'gicdv3_helpers.c' and 'gicrv3_helpers.c' instead of the single helper file previously. Change-Id: I1641bd6d217d6eb7d1228be3c4177b2d556da60a Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* pl011: Use generic console_t data structureAndre Przywara2020-02-251-3/+2
| | | | | | | | | Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I7a23327394d142af4b293ea7ccd90b843c54587c Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* drivers/mhu: derive doorbell base addressAditya Angadi2020-02-071-2/+1
| | | | | | | | | In order to allow the MHUv2 driver to be usable with multiple MHUv2 controllers, use the base address of the controller from the platform information instead of the MHUV2_BASE_ADDR macro. Change-Id: I4dbab87b929fb0568935e6c8b339ce67937f8cd1 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
* Use correct type when reading SCR registerLouis Mayencourt2020-01-281-2/+2
| | | | | | | | The Secure Configuration Register is 64-bits in AArch64 and 32-bits in AArch32. Use u_register_t instead of unsigned int to reflect this. Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* socionext: Unify Platform specific defines for PSCI moduleDeepika Bhavnani2020-01-241-3/+3
| | | | | | | | | | PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: Iad91e99e9d13254de23eb10e5f655253f253cf0d
* spm-mm: Refactor secure_partition.h and its contentsPaul Beesley2019-12-201-6/+6
| | | | | | | | | | | | | | | | | | | Before adding any new SPM-related components we should first do some cleanup around the existing SPM-MM implementation. The aim is to make sure that any SPM-MM components have names that clearly indicate that they are MM-related. Otherwise, when adding new SPM code, it could quickly become confusing as it would be unclear to which component the code belongs. The secure_partition.h header is a clear example of this, as the name is generic so it could easily apply to any SPM-related code, when it is in fact SPM-MM specific. This patch renames the file and the two structures defined within it, and then modifies any references in files that use the header. Change-Id: I44bd95fab774c358178b3e81262a16da500fda26 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* Remove dependency between SPM_MM and ENABLE_SPM build flagsPaul Beesley2019-12-202-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | There are two different implementations of Secure Partition management in TF-A. One is based on the "Management Mode" (MM) design, the other is based on the Secure Partition Client Interface (SPCI) specification. Currently there is a dependency between their build flags that shouldn't exist, making further development harder than it should be. This patch removes that dependency, making the two flags function independently. Before: ENABLE_SPM=1 is required for using either implementation. By default, the SPCI-based implementation is enabled and this is overridden if SPM_MM=1. After: ENABLE_SPM=1 enables the SPCI-based implementation. SPM_MM=1 enables the MM-based implementation. The two build flags are mutually exclusive. Note that the name of the ENABLE_SPM flag remains a bit ambiguous - this will be improved in a subsequent patch. For this patch the intention was to leave the name as-is so that it is easier to track the changes that were made. Change-Id: I8e64ee545d811c7000f27e8dc8ebb977d670608a Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* synquacer: Fix compilation fail for SPM support build configMadhukar Pappireddy2019-07-121-2/+2
| | | | | | | Fix the header file path Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Change-Id: I73a92a3f0049ecbda7eade452405927c04048e01
* Remove MULTI_CONSOLE_API flag and references to itAmbroise Vincent2019-06-281-1/+0
| | | | | | | The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* plat/arm: mhu: make mhu driver genericMasahisa Kojima2019-03-131-1/+1
| | | | | | | | | MHU doorbell driver requires arm platform specific macro "PLAT_CSS_MHU_BASE". Rename it to "PLAT_MHUV2_BASE", so that platforms other than arm can use generic MHU doorbell driver. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
* plat/synquacer: enable SCMI supportMasahisa Kojima2019-03-138-18/+320
| | | | | | | | | | Enable the SCMI protocol support in SynQuacer platform. Aside from power domain, system power and apcore management protocol, this commit adds the vendor specific protocol(0x80). This vendor specific protocol is used to get the dram mapping information from SCP. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
* SPM: Rename SPM_DEPRECATED flag to SPM_MMAntonio Nino Diaz2019-01-221-3/+3
| | | | | | | | | The SPM implementation based on MM is going to be kept for the foreseeable future. Change-Id: I11e96778a4f52a1aa803e7e048d9a7cb24a53954 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Acked-by: Sumit Garg <sumit.garg@linaro.org>
* plat/synquacer: enable SPM supportArd Biesheuvel2019-01-155-3/+214
| | | | | | | | | | Enable the deprecated SPM framework for the SynQuacer platform. It involves creating a memory layout in secure DRAM, and wiring up the SPM infrastructure so that the secure partition payload that is loaded into this region by the SCP firmware is dispatched appropriately. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* plat/synquacer: enable OP-TEE logic only if SPD_opteed is setArd Biesheuvel2019-01-153-6/+4
| | | | | | | | | The logic that initializes the BL32 entry point data structure should only be executed if we are in fact loading OP-TEE, and not if BL32_BASE is set for other reasons (i.e., when enabling SPM) Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* Sanitise includes across codebaseAntonio Nino Diaz2019-01-0410-29/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Standardise header guards across codebaseAntonio Nino Diaz2018-11-084-12/+13
| | | | | | | | | | | | | | | | | | All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* synquacer: Migrate to new interfacesAntonio Nino Diaz2018-09-282-6/+5
| | | | | | | | | | - Remove references to removed build options. - Update Makefile paths. - Migrate to bl31_early_platform_setup2(). Change-Id: I51cbf09a0297ac1ee645a959063238c9d556d8e1 Tested-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Fix MISRA defects in BL31 common codeAntonio Nino Diaz2018-08-301-1/+1
| | | | | Change-Id: I5993b425445ee794e6d2a792c244c0af53640655 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* libc: Fix all includes in codebaseAntonio Nino Diaz2018-08-221-1/+1
| | | | | | | | | The codebase was using non-standard headers. It is needed to replace them by the correct ones so that we can use the new libc headers. Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Merge pull request #1486 from antonio-nino-diaz-arm/an/psci-misradanh-arm2018-07-251-6/+7
|\ | | | | Fix several MISRA defects in PSCI library
| * PSCI: Fix types of definitionsAntonio Nino Diaz2018-07-201-6/+7
| | | | | | | | | | | | | | | | | | Also change header guards to fix defects of MISRA C-2012 Rule 21.1. Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57 Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | synquacer: Enable optional OP-TEE supportSumit Garg2018-07-242-11/+28
|/ | | | | | | | | OP-TEE loading is optional on Developerbox controlled via SCP firmware. To check if OP-TEE is loaded or not, we use DRAM1 region info passed by SCP firmware. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
* synquacer: Add platform makefile and documentationSumit Garg2018-06-211-0/+46
| | | | | | | | | | | | | Add Makefile and plaform definations file. My thanks to Daniel Thompson and Ard Biesheuvel for the bits and pieces I've taken from their earlier work regarding build and deploy steps for Developerbox based on Synquacer SoCs. They deserve much of the credit for this work although, since I assembled and tested things, any blame is probably mine. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Daniel Thompson <daniel.thompson@linaro.org> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* synquacer: Enable PSCI frameworkSumit Garg2018-06-212-0/+198
| | | | | | | | | | | | | | PSCI framework uses SCPI driver to communicate to SCP firmware for various power management operations. Following PSCI operations are supported: - CPU ON - CPU OFF - CPU STANDBY - SYSTEM RESET - SYSTEM OFF Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
* synquacer: Retrieve DRAM info from SCP firmwareArd Biesheuvel2018-06-214-0/+64
| | | | | | | | | Retrieve DRAM info from SCP firmware using SCPI driver. Board supports multiple DRAM slots so its required to fetch DRAM info from SCP firmware and pass this info to UEFI via non-secure SRAM. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
* synquacer: Add SCPI driverSumit Garg2018-06-213-0/+255
| | | | | | | | Add System Control and Power Interface (SCPI) driver which provides APIs for PSCI framework to work. SCPI driver uses MHU driver APIs to communicate with SCP firmware for various system control and power operations. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
* synquacer: Add MHU driverSumit Garg2018-06-215-0/+121
| | | | | | | Add Message Handling Unit (MHU) driver used to communicate among Application Processors (AP) and System Control Processor (SCP). Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
* synquacer: Enable MMU using xlat_tables_v2 librarySumit Garg2018-06-214-0/+71
| | | | | | | | | BL31 runs from SRAM which is a non-coherent memory on synquacer. So enable MMU with SRAM memory marked as Non-Cacheable and mark page tables kept on SRAM as Non-Cacheable via XLAT_TABLE_NC flag. Also add page tables for Device address space. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
* synquacer: Enable System level Generic timerSumit Garg2018-06-212-0/+41
| | | | Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
* synquacer: Enable GICv3 supportSumit Garg2018-06-214-0/+105
| | | | | | | synquacer uses GICv3 compliant GIC500. So enable proper GICv3 driver initialization. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
* synquacer: Enable CCN driver supportSumit Garg2018-06-214-0/+67
| | | | | | | synquacer has CCN-512 interconnect. So enable proper CCN driver initialization. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
* synquacer: Implement topology functionsSumit Garg2018-06-213-0/+58
| | | | | | | These functions describe the layout of the cores and clusters in order to support the PSCI framework. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
* synquacer: Populate BL32 and BL33 entrypointsSumit Garg2018-06-211-0/+63
| | | | | | | As this platform supports direct entry to BL31 and no BL2, so populate BL32 and BL33 entrypoints with static memory load info. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
* synquacer: Enable PL011 UART ConsoleSumit Garg2018-06-213-0/+55
| | | | | Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
* synquacer: Add platform core management helpersSumit Garg2018-06-213-0/+90
| | | | Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
View Lorry Controller Status