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* refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3Arvind Ram Prakash2023-03-152-4/+4
| | | | | | | | | | | | | | | | | | | BL2_AT_EL3 is an overloaded macro which has two uses: 1. When BL2 is entry point into TF-A(no BL1) 2. When BL2 is running at EL3 exception level These two scenarios are not exactly same even though first implicitly means second to be true. To distinguish between these two use cases we introduce new macros. BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2. Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where BL2 runs at EL3 (including four world systems). BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the repository. Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72 Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
* build: always prefix section names with `.`Chris Kay2023-02-202-4/+4
| | | | | | | | | | | | | | | | | Some of our specialized sections are not prefixed with the conventional period. The compiler uses input section names to derive certain other section names (e.g. `.rela.text`, `.relacpu_ops`), and these can be difficult to select in linker scripts when there is a lack of a delimiter. This change introduces the period prefix to all specialized section names. BREAKING-CHANGE: All input and output linker section names have been prefixed with the period character, e.g. `cpu_ops` -> `.cpu_ops`. Change-Id: I51c13c5266d5975fbd944ef4961328e72f82fc1c Signed-off-by: Chris Kay <chris.kay@arm.com>
* fix(synquacer): increase size of BL33Jassi Brar2022-09-211-1/+1
| | | | | | | | Increase the max possible size of BL33 from 1MB to 2MB. For example, edk2 is usually bigger than 1MB Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Change-Id: Idd4762e25e623de145c65f31cf2dfe1fee466a74
* fix: make TF-A use provided OpenSSL binarySalome Thirot2022-08-042-6/+6
| | | | | | | | | | | | | Currently Tf-A uses whatever openssl binary is on the system to sign images. However if OPENSSL_DIR is specified in the build flags this can lead to linking issues as the system binary can end up being linked against shared libraries provided in OPENSSL_DIR/lib if both binaries (the system's and the on in OPENSSL_DIR/bin) are the same version. This patch ensures that the binary used is always the one given by OPENSSL_DIR to avoid those link issues. Signed-off-by: Salome Thirot <salome.thirot@arm.com> Change-Id: Ib534e06ebc8482e4391e376d3791a87968de4a99
* feat(synquacer): add FWU Multi Bank Update supportJassi Brar2022-06-272-1/+32
| | | | | | | | | | | | | | Add FWU Multi Bank Update support. This reads the platform metadata and update the FIP base address so that BL2 can load correct BL3X based on the boot index. Cc: Sumit Garg <sumit.garg@linaro.org> Cc: Masahisa Kojima <masahisa.kojima@linaro.org> Cc: Manish V Badarkhe <manish.badarkhe@arm.com> Cc: Leonardo Sandoval <leonardo.sandoval@linaro.org> Change-Id: I5d96972bc4b3b9a12a8157117e53a05da5ce89f6 Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* feat(synquacer): add TBBR supportJassi Brar2022-06-275-0/+166
| | | | | | | | | | | enable Trusted-Boot for Synquacer platform. Cc: Sumit Garg <sumit.garg@linaro.org> Cc: Masahisa Kojima <masahisa.kojima@linaro.org> Cc: Manish V Badarkhe <manish.badarkhe@arm.com> Cc: Leonardo Sandoval <leonardo.sandoval@linaro.org> Change-Id: I2608b4d573d95d55da1fc5544333e0dbf3f763f2 Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* feat(synquacer): add BL2 supportJassi Brar2022-06-279-8/+407
| | | | | | | | | | | | Add BL2 support by default. Move the legacy mode behind the RESET_TO_BL31 define. Cc: Sumit Garg <sumit.garg@linaro.org> Cc: Masahisa Kojima <masahisa.kojima@linaro.org> Cc: Manish V Badarkhe <manish.badarkhe@arm.com> Cc: Leonardo Sandoval <leonardo.sandoval@linaro.org> Change-Id: Ic490745a7e8f6114172733428ebd6bd6adfcc1ec Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* refactor(synquacer): move common source filesJassi Brar2022-06-271-3/+3
| | | | | | | | | | | | Prepare for introduction of BL2 support by moving reusable files from BL31_SOURCES into PLAT_BL_COMMON_SOURCES Cc: Sumit Garg <sumit.garg@linaro.org> Cc: Masahisa Kojima <masahisa.kojima@linaro.org> Cc: Manish V Badarkhe <manish.badarkhe@arm.com> Cc: Leonardo Sandoval <leonardo.sandoval@linaro.org> Change-Id: I21137cdd40d027cfa77f1dec3598ee85d4873581 Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* Merge "fix(plat/socionext/synquacer): initialise CNTFRQ in Non Secure ↵Madhukar Pappireddy2021-12-092-14/+27
|\ | | | | | | CNTBaseN" into integration
| * fix(plat/socionext/synquacer): initialise CNTFRQ in Non Secure CNTBaseNMasahisa Kojima2021-12-072-14/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The GTimer implemented on SynQuacer has similar issue found on Juno wherein CNTBaseN.CNTFRQ can be written but does not reflect the value of the CNTFRQ register in CNTCTLBase frame. This doesn't follow ARM ARM in that the value updated in CNTCTLBase.CNTFRQ is not reflected in CNTBaseN.CNTFRQ. Hence enable the workaround (applied to Juno) for SynQuacer that updates the CNTFRQ register in the Non Secure CNTBaseN frame. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: I5204fb57f28c0945812814f008c4905ef0882e2b
* | refactor(plat/synquacer): update PSCI system_off handlingMasahisa Kojima2021-12-073-0/+10
|/ | | | | | | | | | | | | | | SynQuacer SoC contains a Cortex-M3 System Control Processor(SCP) which manages system power. This commit modifies the PSCI system_off handling to call SCMI, same as other PSCI calls. System power-off is done by turing off the ATX power supply through GPIO, this operation is transferred to SCP. Note that this commit modifies only the SCMI case, obsolete SCPI implementation is not updated. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: I6c1009e67cccd1eb5d14c338c3df9103d63709dd
* fix(plat/synquacer): update scmi power domain off handlingMasahisa Kojima2021-09-141-0/+8
| | | | | | | | | | | | | In the SCMI power domain off handling, configure GIC to prevent interrupt toward to the core to be turned off, and configure CCN to disable coherency when the cluster is turned off. The same operation is done in SCPI power domain off processing. This commit adds the missing operation in SCMI power domain off handling. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: Ib3523de488500c2e8bdc74e4cb8772a1442d9781
* Don't return error information from console_flushJimmy Brisson2020-10-093-6/+5
| | | | | | | | | | | | | And from crash_console_flush. We ignore the error information return by console_flush in _every_ place where we call it, and casting the return type to void does not work around the MISRA violation that this causes. Instead, we collect the error information from the driver (to avoid changing that API), and don't return it to the caller. Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
* uniphier: increase BL33 max size and GZIP temporary buffer sizeMasahiro Yamada2020-06-293-6/+6
| | | | | | | | | | | | | | | | The current BL33 size is large enough for U-Boot, but we need to increase the limit to use other boot loaders such as edk2. Increase the buffer size used for GZIP decompression too. BL33 max size (UNIPHIER_BL33_MAX_SIZE): 1MB -> 8MB GZIP buffer (UNIPHIER_IMAGE_BUF_SIZE): 1MB -> 8MB Increasing the block buffer size (UNIPHIER_BLOCK_BUF_SIZE) is not required, but I increased it too to make it work more efficiently. Change-Id: I4fa6d795bed9ab9ada7f8f616c7d47076139e3a8 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* xlat_tables_v2: add base table section name parameter for spm_mmMasahisa Kojima2020-06-022-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Core spm_mm code expects the translation tables are located in the inner & outer WBWA & shareable memory. REGISTER_XLAT_CONTEXT2 macro is used to specify the translation table section in spm_mm. In the commit 363830df1c28e (xlat_tables_v2: merge REGISTER_XLAT_CONTEXT_{FULL_SPEC,RO_BASE_TABLE}), REGISTER_XLAT_CONTEXT2 macro explicitly specifies the base xlat table goes into .bss by default. This change affects the existing SynQuacer spm_mm implementation. plat/socionext/synquacer/include/plat.ld.S linker script intends to locate ".bss.sp_base_xlat_table" into "sp_xlat_table" section, but this implementation is no longer available. This patch adds the base table section name parameter for REGISTER_XLAT_CONTEXT2 so that platform can specify the inner & outer WBWA & shareable memory for spm_mm base xlat table. If PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME is not defined, base xlat table goes into .bss by default, the result is same as before. Change-Id: Ie0e1a235e5bd4288dc376f582d6c44c5df6d31b2 Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
* Cleanup the code for TBBR CoT descriptorsManish V Badarkhe2020-05-191-1/+2
| | | | | | | | | | CoT used for BL1 and BL2 are moved to tbbr_cot_bl1.c and tbbr_cot_bl2.c respectively. Common CoT used across BL1 and BL2 are moved to tbbr_cot_common.c. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I2252ac8a6960b3431bcaafdb3ea4fb2d01b79cf5
* uniphier: define PLAT_XLAT_TABLES_DYNAMIC only for BL2Masahiro Yamada2020-04-022-1/+3
| | | | | | | | | | | This is not used in BL31 or Bl32 for this platform. Pass it to BL2_CPPFLAGS instead of defining it for all BL images. This will produce slightly smaller BL31 and Bl32. Change-Id: I66ec5179f8dc5b112e65547335e7dd0a0f4074cd Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* plat: remove redundant =1 from -D optionMasahiro Yamada2020-04-021-2/+2
| | | | | | | | | | | | | | As GCC manual says, -D option defines a macro as 1, if =<value> is omitted. -D <name> Predefine <name> as a macro, with definition 1. The same applied with Clang, too. In the context of -D option, =1 is always redundant. Change-Id: I487489a1ea3eb51e734741619c1e65dab1420bc4 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Pass more -D options to BL*_CPPFLAGS instead of BL*_CFLAGSMasahiro Yamada2020-04-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | Commit d5e97a1d2c79 ("Build: define IMAGE_AT_EL1 or IMAGE_AT_EL3 globally for C files") does not have commit 848a7e8ce1d9 ("Build: introduce per-BL CPPFLAGS and ASFLAGS") as an ancestor because they were pulled almost at the same time. This is a follow-up conversion to be consistent with commit 11a3c5ee7325 ("plat: pass -D option to BL*_CPPFLAGS instead of BL*_CFLAGS"). With this change, the command line option, IMAGE_AT_EL3, will be passed to .S files as well. I remove the definition in include/lib/cpus/aarch64/cpu_macros.S Otherwise, the following error would happen. include/lib/cpus/aarch64/cpu_macros.S:29:0: error: "IMAGE_AT_EL3" redefined [-Werror] Change-Id: I943c8f22356483c2ae3c57b515c69243a8fa6889 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* uniphier: support read-only xlat tablesMasahiro Yamada2020-04-012-0/+20
| | | | | | | | | | | BL2 for this platform uses mmap_add_dynamic_region(), but BL31 and BL32 (TSP) only use static mapping. So, BL31 and BL32 can make the tables read-only after enabling MMU. Enable ALLOW_RO_XLAT_TABLES by default. Change-Id: Ib59c44697163629119888bb6abd47fa144f09ba3 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* uniphier: use enable_mmu() in common functionMasahiro Yamada2020-04-014-5/+2
| | | | | | | | | | Currently, enable_mmu_el1() or enable_mmu_el3() is kept outside the common function because the appropriate one must be chosen. Use enable_mmu() and move it to the common function. Change-Id: If2fb651691a7b6be05674f5cf730ae067ba95d4b Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* TF-A GICv3 driver: Introduce makefileAlexei Fedorov2020-03-302-10/+8
| | | | | | | | | | | | | | | | | This patch moves all GICv3 driver files into new added 'gicv3.mk' makefile for the benefit of the generic driver which can evolve in the future without affecting platforms. The patch adds GICv3 driver configuration flags 'GICV3_IMPL', 'GICV3_IMPL_GIC600_MULTICHIP' and 'GICV3_OVERRIDE_DISTIF_PWR_OPS' described in 'GICv3 driver options' section of 'build-option.rst' document. NOTE: Platforms with GICv3 driver need to be modified to include 'drivers/arm/gic/v3/gicv3.mk' in their makefiles. Change-Id: If055f6770ff20f5dee5a3c99ae7ced7cdcac5c44 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* TF-A GICv3 driver: Separate GICD and GICR accessor functionsAlexei Fedorov2020-03-102-1/+5
| | | | | | | | | | | | This patch provides separation of GICD, GICR accessor functions and adds new macros for GICv3 registers access as a preparation for GICv3.1 and GICv4 support. NOTE: Platforms need to modify to include both 'gicdv3_helpers.c' and 'gicrv3_helpers.c' instead of the single helper file previously. Change-Id: I1641bd6d217d6eb7d1228be3c4177b2d556da60a Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* uniphier: shrink UNIPHIER_ROM_REGION_SIZEMasahiro Yamada2020-03-061-1/+1
| | | | | | | | | | | | Currently, the ROM region is needlessly too large. The on-chip SRAM region of the next SoC will start from 0x04000000, and this will cause the region overlap. Mapping 0x04000000 for the ROM is enough. Change-Id: I85ce0bb1120ebff2e3bc7fd13dc0fd15dfff5ff6 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* uniphier: prepare uniphier_soc_info() for next SoCMasahiro Yamada2020-02-261-3/+10
| | | | | | | | | | | | | | | | The revision register address will be changed in the next SoC. The LSI revision is needed in order to know where the revision register is located, but you need to read out the revision register for that. This is impossible. We need to know the revision register address by other means. Use BL_CODE_BASE, where the base address of the TF image that is currently running. If it is bigger than 0x80000000 (i.e. the DRAM base is 0x80000000), we assume it is a legacy SoC. Change-Id: I9d7f4325fe2085a8a1ab5310025e5948da611256 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge changes from topic "console_t_cleanup" into integrationMark Dykes2020-02-252-19/+12
|\ | | | | | | | | | | | | | | | | | | | | | | | | * changes: marvell: Consolidate console register calls uniphier: Use generic console_t data structure spe: Use generic console_t data structure LS 16550: Use generic console_t data structure stm32: Use generic console_t data structure rcar: Use generic console_t data structure a3700: Use generic console_t data structure 16550: Use generic console_t data structure imx: Use generic console_t data structure
| * uniphier: Use generic console_t data structureAndre Przywara2020-02-252-19/+12
| | | | | | | | | | | | | | | | | | Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: Ia9d996bb45ff3a7f1b240f12fd75805b48a048e9 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | Merge "pl011: Use generic console_t data structure" into integrationMark Dykes2020-02-251-3/+2
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| * pl011: Use generic console_t data structureAndre Przywara2020-02-251-3/+2
| | | | | | | | | | | | | | | | | | Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I7a23327394d142af4b293ea7ccd90b843c54587c Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | Merge "uniphier: make on-chip SRAM region configurable" into integrationSoby Mathew2020-02-251-7/+26
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| * uniphier: make on-chip SRAM region configurableMasahiro Yamada2020-02-121-7/+26
| | | | | | | | | | | | | | | | | | The on-chip SRAM region will be changed in the next SoC. Make it configurable. Also, split the mmap code into a new helper function so that it can be re-used for another boot mode. Change-Id: I89f40432bf852a58ebc9be5d9dec4136b8dc010b Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge changes from topic "uniphier" into integrationSandrine Bailleux2020-02-1411-86/+209
|\ \ | |/ | | | | | | | | | | | | | | | | | | * changes: uniphier: make I/O register region configurable uniphier: make PSCI related base address configurable uniphier: make counter control base address configurable uniphier: make UART base address configurable uniphier: make pinmon base address configurable uniphier: make NAND controller base address configurable uniphier: make eMMC controller base address configurable
| * uniphier: make I/O register region configurableMasahiro Yamada2020-02-125-9/+32
| | | | | | | | | | | | | | | | The I/O register region will be changed in the next SoC. Make it configurable. Change-Id: Iec0cbd1ef2d0703ebc7c3d3082edd73791bbfec9 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * uniphier: make PSCI related base address configurableMasahiro Yamada2020-02-123-21/+51
| | | | | | | | | | | | | | | | The register base address will be changed in the next SoC. Make it configurable. Change-Id: Ibe07bd9db128b0f7e629916cb6ae21ba7984eca9 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * uniphier: make counter control base address configurableMasahiro Yamada2020-02-121-3/+11
| | | | | | | | | | | | | | | | The register base will be changed in the next SoC. Make it configurable. Change-Id: I4a7cf85fe50e4d71db58a3372a71774e43193bd3 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * uniphier: make UART base address configurableMasahiro Yamada2020-02-125-31/+46
| | | | | | | | | | | | | | | | The next SoC supports the same UART, but the register base will be changed. Make it configurable. Change-Id: Ida5c9151b2f3554afd15555b22838437eef443f7 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * uniphier: make pinmon base address configurableMasahiro Yamada2020-02-121-5/+21
| | | | | | | | | | | | | | | | The register base will be changed in the next SoC. Make it configurable. Change-Id: I9fbb6bdd1cf06207618742d4ad7970d911c9bc26 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * uniphier: make NAND controller base address configurableMasahiro Yamada2020-02-123-6/+19
| | | | | | | | | | | | | | | | The next SoC does not support the NAND controller, but make the base address configurable for consistency and future proof. Change-Id: I776e43ff2b0408577919b0b72849c3e1e5ce0758 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * uniphier: make eMMC controller base address configurableMasahiro Yamada2020-02-123-12/+30
| | | | | | | | | | | | | | | | The next SoC supports the same eMMC controller, but the register base will be changed. Make it configurable. Change-Id: I00cb5531bc3d8d49357ad5e922cdd3d785355edf Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge changes from topic "uniphier" into integrationSandrine Bailleux2020-02-133-15/+27
|\ \ | |/ | | | | | | | | | | * changes: uniphier: extend boot device detection for future SoCs uniphier: change block_addressing flag to bool uniphier: change the return value type of .is_usb_boot() to bool
| * uniphier: extend boot device detection for future SoCsMasahiro Yamada2020-02-122-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | The next SoC will have: - No boot swap - SD boot - No USB boot Add new fields to handle this. Change-Id: I772395f2c5dfc612e575b0cbd0657a5fa9611c25 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * uniphier: change block_addressing flag to boolMasahiro Yamada2020-02-121-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | The flag, uniphier_emmc_block_addressing, is boolean logic, so "bool' is more suitable. uniphier_emmc_is_over_2gb() is not boolean - it returns 1 / 0 depending on the card density, or a negative value on failure. Rename it to make it less confusing. Change-Id: Ia646b1929147b644e0df07c46b54ab80548bc3bd Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * uniphier: change the return value type of .is_usb_boot() to boolMasahiro Yamada2020-02-121-5/+5
| | | | | | | | | | | | | | This is boolean logic, so "bool" is more suitable. Change-Id: I439c5099770600a65b8f58390a4c621c2ee487a5 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | drivers/mhu: derive doorbell base addressAditya Angadi2020-02-071-2/+1
|/ | | | | | | | | In order to allow the MHUv2 driver to be usable with multiple MHUv2 controllers, use the base address of the controller from the platform information instead of the MHUV2_BASE_ADDR macro. Change-Id: I4dbab87b929fb0568935e6c8b339ce67937f8cd1 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
* Merge "Use correct type when reading SCR register" into integrationAlexei Fedorov2020-01-301-2/+2
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| * Use correct type when reading SCR registerLouis Mayencourt2020-01-281-2/+2
| | | | | | | | | | | | | | | | The Secure Configuration Register is 64-bits in AArch64 and 32-bits in AArch32. Use u_register_t instead of unsigned int to reflect this. Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | uniphier: make all BL images completely position-independentMasahiro Yamada2020-01-246-35/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This platform supports multiple SoCs. The next SoC will still keep quite similar architecture, but the memory base will be changed. The ENABLE_PIE improves the maintainability and usability. You can reuse a single set of BL images for other SoC/board without re-compiling TF-A at all. This will also keep the code cleaner because it avoids #ifdef around various base addresses. By defining ENABLE_PIE, BL2_AT_EL3, BL31, and BL32 (TSP) are really position-independent now. You can load them anywhere irrespective of their link address. Change-Id: I8d5e3124ee30012f5b3bfa278b0baff8efd2fff7 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | uniphier: make uniphier_mmap_setup() work with PIEMasahiro Yamada2020-01-245-24/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BL2_BASE, BL31_BASE, and BL32_BASE are defined in platform_def.h, that is, determined at link-time. On the other hand, BL2_END, BL31_END, and BL32_END are derived from the symbols produced by the linker scripts. So, they are fixed-up at run-time if ENABLE_PIE is enabled. To make it work in a position-indepenent manner, use BL_CODE_BASE and BL_END, both of which are relocatable. Change-Id: Ic179a7c60eb64c5f3024b178690b3ac7cbd7521b Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | uniphier: pass SCP base address as a function parameterMasahiro Yamada2020-01-243-8/+6
| | | | | | | | | | | | | | | | | | | | | | Currently, UNIPHIER_SCP_BASE is hard-coded in uniphier_scp_start(), which is not handy for PIE. Towards the goal of making this really position-independent, pass in image_info->image_base. Change-Id: I88e020a1919c607b1d5ce70b116201d95773bb63 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | uniphier: set buffer offset and length for io_block dynamicallyMasahiro Yamada2020-01-245-47/+42
| | | | | | | | | | | | | | | | | | | | | | Currently, the .buffer field in io_block_dev_spec is statically set, which is not handy for PIE. Towards the goal of making this really position-independent, set the buffer length and length in the uniphier_io_block_setup() function. Change-Id: I22b20d7b58d6ffd38f64f967a2820fca4bd7dade Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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