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* Merge "docs(prerequisites): update software and libraries prerequisites" ↵HEADmasterintegrationBipin Ravi2023-05-161-3/+3
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| * docs(prerequisites): update software and libraries prerequisitesGovindraj Raja2023-05-161-3/+3
| | | | | | | | | | | | | | | | | | | | | | Update to use the following software: - mbed TLS == 3.4.0 - (DTC) >= 1.4.7 - Ubuntu 22.04 for builds. Signed-off-by: Govindraj Raja <govindraj.raja@arm.com> Change-Id: I384aab4dfee9cae9453eebf4091abe82ef9ccfaa
* | Merge "fix(tegra210): mark bits [23:17] as zero for Fast SMCs" into integrationManish Pandey2023-05-161-4/+5
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| * | fix(tegra210): mark bits [23:17] as zero for Fast SMCsKalyani Chidambaram Vaidyanathan2023-05-121-4/+5
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | Per SMCCC documentation, bits [23:17] must be zero for Fast SMCs. Other values are reserved for future use. Ensure that these bits are zeroes for TEGRA_SIP_PMC_COMMANDS. Commit f8a35797 introduced a check to return error if these bits are not zero, thus breaking Tegra210 platforms. This patch fixes the anomaly. Change-Id: I19edc3b33c999a6fee6b86184233fba146316466 Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | Merge changes from topic "ja/mem_share_doc" into integrationManish Pandey2023-05-162-4/+244
|\ \ | | | | | | | | | | | | | | | * changes: docs(spm): threat model for memory sharing functionality docs(spm): add memory sharing documentation
| * | docs(spm): threat model for memory sharing functionalityJ-Alves2023-05-121-4/+182
| | | | | | | | | | | | | | | | | | | | | | | | Update the SPM threat model with information about FF-A v1.1 memory sharing functionality. Change-Id: I65ea0d53aba8ac2f8432539968ceaab6be109ac8 Signed-off-by: J-Alves <joao.alves@arm.com>
| * | docs(spm): add memory sharing documentationJ-Alves2023-05-121-0/+62
| |/ | | | | | | | | | | | | | | | | Add documentation that explains implementation specific relevant information from the update done to FF-A v1.1 memory sharing in Hafnium. Change-Id: Ifc3c6b86c0545d53331207b017b990427ee84f2d Signed-off-by: J-Alves <joao.alves@arm.com>
* | Merge changes from topics "plat_tests_scalability", "sb/tc-plat-tests" into ↵Sandrine Bailleux2023-05-165-38/+82
|\ \ | |/ |/| | | | | | | | | | | | | | | | | integration * changes: test(tc): unify platform tests traces test(tc): return test failures count for tfm-testsuite test(tc): move platform tests in their own function test(tc): centralize platform error handling refactor(tc): define PLATFORM_TESTS for scale
| * test(tc): unify platform tests tracesSandrine Bailleux2023-05-151-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | Add some traces at the start and end of platform tests. These traces are the same regardless of the set of platform tests we run (NV counter tests / TF-M testsuite / future set of tests). This makes it easier to integrate these tests in the CI because we can now have a unified "expect" script for all platform tests, instead of having one dedicated "expect" script for each possible set of tests. Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Change-Id: I5ec30a7a25d8a9a4a90e3338a9789acff7ad4843
| * test(tc): return test failures count for tfm-testsuiteSandrine Bailleux2023-05-151-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | When running the "tfm-testsuite" set of platform tests, we now count the number of failed tests (in addition to printing a test summary) and report that back to the caller, i.e. tc_bl31_common_platform_setup(). This will be useful to consolidate the tests failure reporting code in a subsequent patch. Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Change-Id: I8e51f03869f3b2f264b6581b3bd2a53be0198057
| * test(tc): move platform tests in their own functionSandrine Bailleux2023-05-151-4/+11
| | | | | | | | | | | | | | | | | | | | This is a bit cleaner, as it avoids cluttering the normal boot execution path. It also gives us the opportunity to mark the tests function with the __dead2 attribute, which inform both the compiler and the developer that the test function never returns (since it suspends booting). Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Change-Id: I082a34a840ef791a2ac4c1f59b19b32aeb0a9ec7
| * test(tc): centralize platform error handlingSandrine Bailleux2023-05-154-15/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Note that this change only affects the platform tests execution path. It has no impact on the normal boot flow. Make individual test functions propagate an error code, instead of calling the platform error handler at the point of failure. The latter is now the responsibility of the caller - in this case tc_bl31_common_platform_setup(). Note that right now, tc_bl31_common_platform_setup() does not look at the said error code but this initial change opens up an opportunity to centralize any error handling in tc_bl31_common_platform_setup(), which we will seize in subsequent patches. Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Change-Id: Ib282b64039e0b1ec6e6d29476fbaa2bcd33cb0c7
| * refactor(tc): define PLATFORM_TESTS for scalelaurenw-arm2023-05-052-18/+22
| | | | | | | | | | | | | | | | | | For scalability when we add more tests in the future, add PLATFORM_TESTS macro when specific test flags, i.e. PLATFORM_TEST_NV_COUNTERS, are defined. Change-Id: Icb875a171dde673fca9fcf66624ac55383e7b641 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
* | Merge "docs(psci): expound runtime instrumentation docs" into integrationv2.9-rc0Manish Pandey2023-05-113-1/+175
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| * | docs(psci): expound runtime instrumentation docsHarrison Mutai2023-05-113-1/+175
| | | | | | | | | | | | | | | Change-Id: I3c30b44d4196c30fd07373282150e543959fce1a Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
* | | Merge changes from topic "ms/external_deps" into integrationJoanna Farley2023-05-115-12/+25
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | * changes: feat(libc): add %c to printf/snprintf feat(compiler-rt): update source files chore(libfdt): update to v1.7.0 source files
| * | | feat(libc): add %c to printf/snprintfMaksims Svecovs2023-05-112-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds %c support for printf and snprintf to print one character. Required by most recent MbedTLS 3.4.0. Change-Id: I4d9b2725127a929d58946353324f99ff22b3b28b Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
| * | | feat(compiler-rt): update source filesMaksims Svecovs2023-05-112-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the compiler-rt source files to the tip of the llvm-project [1] [1]: https://github.com/llvm/llvm-project/commit/d9683a7 Change-Id: Icec9ec73094a2b39b0240fc8253c36e7485d3a98 Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
| * | | chore(libfdt): update to v1.7.0 source filesMaksims Svecovs2023-05-111-8/+12
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | Update libfdt to source files from v1.7.0 release. Upstream commit: https://github.com/dgibson/dtc/commit/039a99414e778332d8f9c04cbd3072e1dcc62798 Change-Id: I7e0475d2ddb819691f476e1753d1c899f8d7c278 Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
* | | Merge "feat(optee): add device tree for coreboot table" into integrationManish Pandey2023-05-114-1/+115
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| * | | feat(optee): add device tree for coreboot tableJeffrey Kardatzke2023-05-114-1/+115
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds creation of a device tree that will be passed to OP-TEE. Currently that device tree only contains the coreboot table per the Linux coreboot device tree specification. This device tree is then passed to OP-TEE so it can extract the CBMEM console information from the coreboot table for logging purposes. Signed-off-by: Jeffrey Kardatzke <jkardatzke@google.com> Change-Id: I6a26d335e16f7226018c56ad571cca77b81b0f6a
* | | Merge "fix(n1sdp): add platform-specific power domain functions" into ↵Manish Pandey2023-05-114-1/+49
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| * | | fix(n1sdp): add platform-specific power domain functionsWerner Lewis2023-05-034-1/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 4d8c18196378824e388cf31ef991ba8fbbb09cbf added a redistributor power off to resolve an error on N1SDP/Morello. Prior to this fix, turning off both cores in a cluster would cause a hang when powering back on either core. This change introduced issues on other platforms with a different GIC implementation, and was reverted in commit 60719e4e0965aead49d927f12bf2a37bd2629012. This commit uses the previous fix in platform-specific implementations of power domain off/suspend functions. Signed-off-by: Werner Lewis <werner.lewis@arm.com> Change-Id: I52c463646c494fe931ff4ce47afb940a56978fcd
* | | | Merge "fix(morello): add platform-specific power domain functions" into ↵Manish Pandey2023-05-114-0/+48
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| * | | fix(morello): add platform-specific power domain functionsWerner Lewis2023-05-034-0/+48
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 4d8c18196378824e388cf31ef991ba8fbbb09cbf added a redistributor power off to resolve an error on N1SDP/Morello. Prior to this fix, turning off both cores in a cluster would cause a hang when powering back on either core. This change introduced issues on other platforms with a different GIC implementation, and was reverted in commit 60719e4e0965aead49d927f12bf2a37bd2629012. This commit uses the previous fix in platform-specific implementations of power domain off/suspend functions. Signed-off-by: Werner Lewis <werner.lewis@arm.com> Change-Id: Ib7689a5e08ada3862406fa92019a6f0bcfb48d79
* | | Merge "fix: increase BL32 limit" into integrationManish Pandey2023-05-111-2/+2
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| * | | fix: increase BL32 limitManish V Badarkhe2023-05-111-2/+2
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | BL32_LIMIT has been increased from 2MB to 4MB to accommodate the latest tee.bin (it is around ~2.1MB). Change-Id: I47b770bf23c23d38931a2b3316d076b829338d70 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Co-developed-by: Juan Pablo Conde <juanpablo.conde@arm.com>
* | | Merge "fix(spmd): fix build error with spmd" into integrationMadhukar Pappireddy2023-05-115-9/+9
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| * | | fix(spmd): fix build error with spmdGovindraj Raja2023-05-105-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently when we build with 'SPD=spmd SPMD_SPM_AT_SEL2=0' options, this causes a build failure as 'plat_spmd_handle_group0_interrupt' is called irrespective of 'SPMD_SPM_AT_SEL2' usage in 'spmd_group0_interrupt_handler_nwd' So make 'plat_spmd_handle_group0_interrupt' dummy implementation available just when spmd is enabled and SPMC_AT_EL3 is disabled. Change-Id: Iaccd38faab81671c98f9165f318145187dca9bc2 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
* | | | Merge "fix(psci): do not panic on illegal MPIDR" into integrationManish Pandey2023-05-102-6/+6
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| * | | | fix(psci): do not panic on illegal MPIDRAndre Przywara2023-05-032-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 66327414fb1e ("fix(psci): potential array overflow with cpu on") changed an assert in the PSCI library's psci_cpu_on_start() function to a runtime error message, followed by a panic. This does not seem right for two reasons: - We must not panic() triggered by conditions influenced by lower EL callers. If non-secure world provides illegal arguments to a PSCI call, we can easily detect this and return -PSCI_E_INVALID_PARAMS, as the PSCI spec demands. In fact this is done already, which brings us to the next reason: - psci_cpu_on_start() is effectively a function private to the PSCI library: its prototype is in psci_private.h. It's just not static because it lives in a different code file from the main PSCI code. We check for illegal MPID values already in psci_cpu_on(), and return an error value to the caller, as we should. This function is the ONLY caller of psci_cpu_on_start(), so there is no way we get an illegal target_cpu argument into this function. An assert() is thus the proper way to check for this. Mostly revert the patch mentioned above, just extending the assert so that it does also check for not exceeding the array boundaries. To harden the code, add a check against PLATFORM_MAX_CORE_COUNT in psci_validate_mpidr(), and return with the proper PSCI error code if this number is exceeded. This also fixes the sun50i_a64 build with DEBUG=1, which exceeded an SRAM limit due to the error message. Change-Id: I48fc58d96b0173da5b934750f4cadf7884ef5e42 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | | | Merge "build(fpga): reduce cpu_libs to tc and neoverse" into integrationManish V Badarkhe2023-05-101-18/+14
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| * | | | | build(fpga): reduce cpu_libs to tc and neoverseDaniel Boulby2023-05-101-18/+14
| | |/ / / | |/| | | | | | | | | | | | | | | | | | Change-Id: I20e88d5e712dafa7364b7932b8b4aaa9051bea55 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
* | | | | Merge "docs: update release and code freeze dates" into integrationJoanna Farley2023-05-101-1/+3
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| * | | | | docs: update release and code freeze datesHarrison Mutai2023-05-051-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Harrison Mutai <harrison.mutai@arm.com> Change-Id: If782bd337d10213cb74503f4ea54ed304d6e4c34
* | | | | | Merge "fix(pmu): unconditionally save PMCR_EL0" into integrationManish Pandey2023-05-104-78/+7
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| * | | | | fix(pmu): unconditionally save PMCR_EL0Boyan Karatotev2023-05-054-78/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reading back a RES0 bit does not necessarily mean it will be read as 0. The Arm ARM explicitly warns against doing this. The PMU initialisation code tries to set such bits to 1 (in MDCR_EL3) regardless of whether they are in use or are RES0, checking their value could be wrong and PMCR_EL0 might not end up being saved. Save PMCR_EL0 unconditionally to prevent this. Remove the security state change as the outgoing state is not relevant to what the root world context should look like. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: Id43667d37b0e2da3ded0beaf23fa0d4f9013f470
* | | | | | Merge changes I5bb43cb0,I6aebe2ca,Ib59df16a,I9d037ab2,I9df5a465, ... into ↵Manish V Badarkhe2023-05-097-28/+50
|\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | integration * changes: fix(msm8916): add timeout for crash console TX flush style(msm8916): use size macros feat(msm8916): expose more timer frames fix(msm8916): drop unneeded initialization of CNTACR build(msm8916): disable unneeded workarounds fix(msm8916): flush dcache after writing msm8916_entry_point fix(msm8916): print \r before \n on UART console
| * | | | | | fix(msm8916): add timeout for crash console TX flushStephan Gerhold2023-05-092-14/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Resetting the UART DM controller while there are still remaining characters in the FIFO often results in corruption on the UART receiver side. To avoid this the msm8916 crash console implementation tries to wait until the TX FIFO is empty. Unfortunately this might spin forever if the transmitter was disabled before it has fully finished transmitting. In this case the TXEMT bit console_uartdm_core_flush is waiting for will never get set. There seems to be no good way to detect if the transmitter is actually enabled via the status registers. However, the TX FIFO is fairly small and should not take too long to get flushed, so fix this by simply limiting the amount of iterations with a short timeout. Move the code to console_uartdm_core_init to ensure that this always happens before resetting the transmitter (also during initialization). Change-Id: I5bb43cb0b6c029bcd15e253d60d36c0b310e108b Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
| * | | | | | style(msm8916): use size macrosStephan Gerhold2023-05-092-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the pre-defined size macros (SZ_*) for more clarity and to avoid having to add comments to each size represented by hexadecimal numbers. Change-Id: I6aebe2caf1365279670955b9b507dec7d7b04457 Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
| * | | | | | feat(msm8916): expose more timer framesStephan Gerhold2023-05-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The memory-mapped generic timer on msm8916 has 7 timer frames, but currently only one is exposed for usage in the non-secure world. The platform port is currently only designed to be used as minimal PSCI implementation, without secure world that could make use of the other timer frames. Let's make all of them available to the normal world. If needed this could still be changed later by reserving some timer frames conditionally to a specific SPD being enabled in the build. Change-Id: Ib59df16aa1fd3dbc875ab6369c133737830c98c6 Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
| * | | | | | fix(msm8916): drop unneeded initialization of CNTACRStephan Gerhold2023-05-091-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Normal world software is responsible to initialize CNTACR as needed. There is no existing software for msm8916 that depends on having this initialization in BL31 so drop it before anything starts to rely on it. Related issue: https://github.com/ARM-software/tf-issues/issues/170 Change-Id: I9d037ab218c0c1c8a5d5523722013eba531f4728 Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
| * | | | | | build(msm8916): disable unneeded workaroundsStephan Gerhold2023-05-091-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Cortex-A53 cores used in the msm8916 platform are not affected by CVE-2017-5715 and CVE-2022-23960, so disable the workarounds for them to drop the unused code from the compiled binary. Change-Id: I9df5a4657c4fd90702b4db4e82d4ee1a2f60303c Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
| * | | | | | fix(msm8916): flush dcache after writing msm8916_entry_pointStephan Gerhold2023-05-091-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | msm8916_entry_point is read with caches off (and even from two different physical addresses when read through the "boot remapper"), so it should be flushed to RAM after writing it. Change-Id: I5c8193954bb28043b0a46fb2038f629bd8796c74 Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
| * | | | | | fix(msm8916): print \r before \n on UART consoleStephan Gerhold2023-05-091-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UART drivers in TF-A are expected to print \r before \n. Some terminal emulators expect \r\n as line endings by default so not doing this causes broken line breaks. Change-Id: I271a35a7c6907441bc71713b0b6a1da19da96878 Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
* | | | | | | Merge changes I1bfa797e,I0ec7a70e into integrationManish Pandey2023-05-09110-137/+137
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: fix(tree): correct some typos fix(rockchip): use semicolon instead of comma
| * | | | | | | fix(tree): correct some typosElyes Haouas2023-05-09109-136/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | found using codespell (https://github.com/codespell-project/codespell). Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373
| * | | | | | | fix(rockchip): use semicolon instead of commaElyes Haouas2023-05-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use semicolon insted of comma at the end of line. Change-Id: I0ec7a70ec659333c98d586f7bebd5d91bd6c6cc1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
* | | | | | | | Merge changes from topic "mp/feat_ras" into integrationManish Pandey2023-05-0930-137/+177
|\ \ \ \ \ \ \ \ | |_|/ / / / / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED refactor(ras): replace RAS_EXTENSION with FEAT_RAS
| * | | | | | | refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKEDAndre Przywara2023-05-099-59/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_RAS to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (FEAT_RAS=2), by splitting is_armv8_2_feat_ras_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access RAS related registers. Also move the context saving code from assembly to C, and use the new is_feat_ras_supported() function to guard its execution. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I30498f72fd80b136850856244687400456a03d0e Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
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