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* Merge changes I1bfa797e,I0ec7a70e into integrationManish Pandey2023-05-091-1/+1
|\ | | | | | | | | | | * changes: fix(tree): correct some typos fix(rockchip): use semicolon instead of comma
| * fix(tree): correct some typosElyes Haouas2023-05-091-1/+1
| | | | | | | | | | | | | | found using codespell (https://github.com/codespell-project/codespell). Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373
* | Merge changes from topic "mp/feat_ras" into integrationManish Pandey2023-05-091-1/+2
|\ \ | | | | | | | | | | | | | | | * changes: refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED refactor(ras): replace RAS_EXTENSION with FEAT_RAS
| * | refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKEDAndre Przywara2023-05-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_RAS to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (FEAT_RAS=2), by splitting is_armv8_2_feat_ras_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access RAS related registers. Also move the context saving code from assembly to C, and use the new is_feat_ras_supported() function to guard its execution. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I30498f72fd80b136850856244687400456a03d0e Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
| * | refactor(ras): replace RAS_EXTENSION with FEAT_RASManish Pandey2023-05-091-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current usage of RAS_EXTENSION in TF-A codebase is to cater for two things in TF-A : 1. Pull in necessary framework and platform hooks for Firmware first handling(FFH) of RAS errors. 2. Manage the FEAT_RAS extension when switching the worlds. FFH means that all the EAs from NS are trapped in EL3 first and signaled to NS world later after the first handling is done in firmware. There is an alternate way of handling RAS errors viz Kernel First handling(KFH). Tying FEAT_RAS to RAS_EXTENSION build flag was not correct as the feature is needed for proper handling KFH in as well. This patch breaks down the RAS_EXTENSION flag into a flag to denote the CPU architecture `ENABLE_FEAT_RAS` which is used in context management during world switch and another flag `RAS_FFH_SUPPORT` to pull in required framework and platform hooks for FFH. Proper support for KFH will be added in future patches. BREAKING CHANGE: The previous RAS_EXTENSION is now deprecated. The equivalent functionality can be achieved by the following 2 options: - ENABLE_FEAT_RAS - RAS_FFH_SUPPORT Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I1abb9ab6622b8f1b15712b12f17612804d48a6ec
* | Merge changes from topic "srm/Errata_ABI_El3" into integrationMadhukar Pappireddy2023-05-092-0/+65
|\ \ | |/ |/| | | | | | | | | | | | | * changes: docs(errata_abi): document the errata abi changes feat(fvp): enable errata management interface fix(cpus): workaround platforms non-arm interconnect refactor(errata_abi): factor in non-arm interconnect feat(errata_abi): errata management firmware interface
| * feat(fvp): enable errata management interfaceSona Mathew2023-05-052-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Errata ABI feature specific build flag, flag to enable CPUs in the cpu list, flags to test non-arm interconnect based errata flags when enabled from a platform level. Added to the FVP platform makefile to test the errata abi feature implementation. The flags to enable CPUs in the cpu list will be removed once synchronized with the errata framework. Change-Id: I30877a22ac1348906a6ddfb26f9e8839912d3572 Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
* | Merge "feat(fvp): introduce PLATFORM_TEST_RAS_FFH config" into integrationManish Pandey2023-05-093-3/+72
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| * feat(fvp): introduce PLATFORM_TEST_RAS_FFH configManish Pandey2023-05-043-3/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | While doing RAS related tests there were few patches related with fault injection and handling were applied through CI hooks. These patches were invisible as they were applied and removed after the build is done. This patch introduces build macro PLATFORM_TEST_RAS_FFH and moves the patches applied through CI under this. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Iddba52f3ebf21f575a473e50c607a944391156b9
* | Merge "feat(fvp): define ns memory in the SPMC manifest" into integrationMadhukar Pappireddy2023-05-041-4/+12
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| * feat(fvp): define ns memory in the SPMC manifestJ-Alves2023-05-031-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPMC (Hafnium) looks for secure and non-secure ranges in its manifest. Those relate with ranges that can be used by SPs in their FF-A manifests. The NS memory that is not used by SPs will be assigned to the NWd, for it to share memory with SPs as needed. Thus, this limits the memory the NWd can share with SPs, to prevent NWD VMs from sharing memory that belongs to other critical components. Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: Iad03eb138a57068fbb18c53141bdf6bf9c171b28
* | Merge changes from topic "mp/group0_support" into integrationOlivier Deprez2023-05-032-0/+21
|\ \ | | | | | | | | | | | | | | | | | | | | | * changes: docs(spm): support for handling Group0 interrupts feat(spmd): introduce platform handler for Group0 interrupt feat(spmd): add support for FFA_EL3_INTR_HANDLE_32 ABI feat(spmd): register handler for group0 interrupt from NWd
| * | feat(spmd): introduce platform handler for Group0 interruptMadhukar Pappireddy2023-05-012-0/+21
| |/ | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a handler for FVP platform to triage Group0 secure interrupts. Currently, it is empty but serves as a placeholder for future Group0 interrupt sources. Moreover, this patch also provides a dummy implementation of the above mentioned platform hook for QEMU, corstone100, n1sdp and hikey960 ports. Change-Id: I01d3451408f47ac313b0af74046cce89f89b85bb Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | Merge "fix(sme): disable SME for SPD=spmd" into integrationManish Pandey2023-05-021-1/+3
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| * fix(sme): disable SME for SPD=spmdJayanth Dodderi Chidanand2023-04-281-1/+3
| | | | | | | | | | | | | | | | SPMD is not compatible with ENABLE_SME_FOR_NS. Hence disable SME when SPD=spmd Change-Id: I8bcf2493819718732563f9db69f7186ac7437637 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* | Merge "feat(fvp): introduce PLATFORM_TEST_EA_FFH config" into integrationManish Pandey2023-04-282-0/+62
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| * | feat(fvp): introduce PLATFORM_TEST_EA_FFH configManish Pandey2023-04-282-0/+62
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | FVP currently does not have proper handler to do Firmware First Handling (FFH) of lower EL External aborts and it ends up in EL3 panic. To test the scenarios sensibly we need a proper handling when the FVP is under test so that we do not change the default behavior. Introduce PLATFORM_TEST_EA_FFH config which will be enabled in CI scripts and implement a proper handling for Sync EA and SErrors from lower EL. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ib130154206b17f72c49c9f07de2d92f35a97ab0b
* | Merge "feat(sme): enable SME2 functionality for NS world" into integrationManish Pandey2023-04-281-0/+1
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| * | feat(sme): enable SME2 functionality for NS worldJayanth Dodderi Chidanand2023-04-271-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FEAT_SME2 is an extension of FEAT_SME and an optional feature from v9.2. Its an extension of SME, wherein it not only processes matrix operations efficiently, but also provides outer-product instructions to accelerate matrix operations. It affords instructions for multi-vector operations. Further, it adds an 512 bit architectural register ZT0. This patch implements all the changes introduced with FEAT_SME2 to ensure that the instructions are allowed to access ZT0 register from Non-secure lower exception levels. Additionally, it adds support to ensure FEAT_SME2 is aligned with the existing FEATURE DETECTION mechanism, and documented. Change-Id: Iee0f61943304a9cfc3db8f986047b1321d0a6463 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* | build(fvp): reduce the number of cpu libraries included by defaultBoyan Karatotev2023-04-261-18/+8
|/ | | | | | | | | | | | | | The fvp build includes a very large number of cpus so that it can run on a wide range of models. One config (HW_ASSISTED_COHERENCY=1 CTX_INCLUDE_AARCH32_REGS=0) includes an unusually large number of cpus. Well, the list is quite arbitrary and incomplete. As we're currently out of BL31 space on the fvp, remove all that are not routinely run in the CI to buy us some time. Also use the opportunity to reorder the list into something searchable. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I8c6cad41327451edf0d3a0e92c43d6c72c254aac
* refactor(cpufeat): enable FEAT_DIT for FEAT_STATE_CHECKEDAndre Przywara2023-04-251-0/+1
| | | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_DIT to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_DIT=2), by splitting is_armv8_4_dit_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed). We use ENABLE_DIT in two occassions in assembly code, where we just set the DIT bit in the DIT system register. Protect those two cases by reading the CPU ID register when ENABLE_DIT is set to 2. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I506d352f18e23c60db8cdf08edb449f60adbe098 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* Merge "feat(gcs): support guarded control stack" into integrationBipin Ravi2023-04-251-0/+1
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| * feat(gcs): support guarded control stackMark Brown2023-04-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Arm v9.4 introduces support for Guarded Control Stack, providing mitigations against some forms of RPO attacks and an efficient mechanism for obtaining the current call stack without requiring a full stack unwind. Enable access to this feature for EL2 and below, context switching the newly added EL2 registers as appropriate. Change the FVP platform to default to handling this as a dynamic option so the right decision can be made by the code at runtime. Signed-off-by: Mark Brown <broonie@kernel.org> Change-Id: I691aa7c22e3547bb3abe98d96993baf18c5f0e7b
* | fix(fvp): correct ehf priority for SPM_MMManish Pandey2023-04-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | PLAT_SP_PRI is used by SPM_MM and it is assigned same value as RAS priority. Which is not allowed by exception handling framework and causes build failure if both SPM_MM and RAS is enabled. To fix this problem assign SP a different priority than RAS. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Iff64ac547f0966c0d94ac7c3ab0eb1e3151fb314
* | feat(fvp): add Event Log maximum size property in DTManish V Badarkhe2023-04-183-3/+7
|/ | | | | | | | | | | | Updated the code to get and set the 'tpm_event_log_max_size' property in the event_log.dtsi. In this change, the maximum Event Log buffer size allocated by BL1 is passed to BL2, rather than both relying on the maximum Event Log buffer size macro. Change-Id: I7aa6256390872171e362b6f166f3f7335aa6e425 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
* feat(pie/por): support permission indirection and overlayMark Brown2023-04-121-0/+4
| | | | | | | | | | | | | | | | | | | Arm v8.9 introduces a series of features providing a new way to set memory permissions. Instead of directly encoding the permissions in the page tables the PTEs contain indexes into an array of permissions stored in system registers, allowing greater flexibility and density of encoding. Enable access to these features for EL2 and below, context switching the newly added EL2 registers as appropriate. Since all of FEAT_S[12]P[IO]E are separately discoverable we have separate build time options for enabling them, but note that there is overlap in the registers that they implement and the enable bit required for lower EL access. Change the FVP platform to default to handling them as dynamic options so the right decision can be made by the code at runtime. Signed-off-by: Mark Brown <broonie@kernel.org> Change-Id: Icf89e444e39e1af768739668b505661df18fb234
* Merge "fix(fvp): work around DRTM_SUPPORT BL31 progbits exceeded" into ↵Manish V Badarkhe2023-04-061-0/+4
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| * fix(fvp): work around DRTM_SUPPORT BL31 progbits exceededBoyan Karatotev2023-04-041-0/+4
| | | | | | | | | | | | | | | | | | | | | | Just like the tspd, DRTM support pulls in a lot of code which can't fit into SRAM with everything else the fvp is including. Luckily, testing this feature is only done on v8.0 models, meaning all feature related code can be excluded for this run, saving space. The benefit of doing it this way is that the test can continue running unaltered in the interim. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: Iced2089837622fea49c10ae403c653dd1f331ca3
* | feat(cpus): add support for blackhawk cpuGovindraj Raja2023-04-041-1/+2
| | | | | | | | | | | | | | | | | | Add basic CPU library code to support the Blackhawk CPU, BlackHawk core is based out of Hunter ELP core, so overall library code was adapted based on that. Change-Id: I4750e774732218ee669dceb734cd107f46b78492 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
* | feat(cpus): add support for chaberton cpuGovindraj Raja2023-04-041-1/+2
| | | | | | | | | | | | | | | | | | Add basic CPU library code to support the Chaberton CPU, Chaberton cores are based out of Hunter core, so overall library code was adapted based on that. Change-Id: I58321c77f2c364225a764da6fa65656d1bec33f1 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
* | fix(fvp): incorrect UUID name in FVP tb_fw_configRob Hughes2023-04-041-2/+2
|/ | | | | | Signed-off-by: Rob Hughes <robert.hughes@arm.com> Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: I557bca7dd32c3be084bbba11d84dfa2818cb6791
* fix(fvp): work around BL31 progbits exceededBoyan Karatotev2023-04-031-47/+51
| | | | | | | | | | | | | | | | | | | | | It is useful to have a single build for the FVP that includes as much stuff as possible. Such a build allows a single TF-A build to be used on a wide variety of fvp command lines. Unfortunately, the fvp also has a (somewhat arbitrary) SRAM limit and enabling a bunch of stuff overruns what is available. To workaround this limit, don't enable everything for all configurations. The offending configuration is when tsp is enabled, so try to slim the binary down only when building with it. As this doesn't solve the issue of running out of space for BL31, update the linker error to give some clue as to what has (likely) caused it while more permanent fixes are found. Also add FEAT_RNG to the mix as it got missed in the commotion. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: Icb27cc837c2d90ca182693e9b3121b51383d51fd
* feat(cpufeat): enable FEAT_SME for FEAT_STATE_CHECKEDJayanth Dodderi Chidanand2023-03-281-0/+11
| | | | | | | | | | | | | | Add support for runtime detection (ENABLE_SME_FOR_NS=2), by splitting feat_sme_supported() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we do SME specific setup. Change the FVP platform default to the now supported dynamic option (=2),so the right decision can be made by the code at runtime. Change-Id: Ida9ccf737db5be20865b84f42b1f9587be0626ab Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* Merge changes from topic "psci-osi" into integrationManish Pandey2023-03-283-0/+20
|\ | | | | | | | | | | | | | | | | | | | | * changes: feat(sc7280): add support for PSCI_OS_INIT_MODE feat(fvp): enable support for PSCI OS-initiated mode feat(psci): update PSCI_FEATURES feat(psci): add support for OS-initiated mode feat(psci): add support for PSCI_SET_SUSPEND_MODE build(psci): add build option for OS-initiated mode docs(psci): add design proposal for OS-initiated mode
| * feat(fvp): enable support for PSCI OS-initiated modeWing Li2023-03-233-0/+20
| | | | | | | | | | Change-Id: I4cd6d2bd7ec7f581bd525d5323a3b54e855e2e51 Signed-off-by: Wing Li <wingers@google.com>
* | refactor(amu): use new AMU feature check routinesAndre Przywara2023-03-271-0/+1
| | | | | | | | | | | | | | | | | | The AMU extension code was using its own feature detection routines. Replace them with the generic CPU feature handlers (defined in arch_features.h), which get updated to cover the v1p1 variant as well. Change-Id: I8540f1e745d7b02a25a6c6cdf2a39d6f5e21f2aa Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | refactor(amu): unify ENABLE_AMU and ENABLE_FEAT_AMUv1Andre Przywara2023-03-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far we have the ENABLE_AMU build option to include AMU register handling code for enabling and context switch. There is also an ENABLE_FEAT_AMUv1 option, solely to protect the HAFGRTR_EL2 system register handling. The latter needs some alignment with the new feature scheme, but it conceptually overlaps with the ENABLE_AMU option. Since there is no real need for two separate options, unify both into a new ENABLE_FEAT_AMU name in a first step. This is mostly just renaming at this point, a subsequent patch will make use of the new feature handling scheme. Change-Id: I97d8a55bdee2ed1e1509fa9f2b09fd0bdd82736e Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | Merge changes from topic "feat_state_part4" into integrationManish Pandey2023-03-271-1/+7
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: refactor(cpufeat): enable FEAT_RNG for FEAT_STATE_CHECKED refactor(cpufeat): align FEAT_SEL2 to new feature handling refactor(cpufeat): enable FEAT_NV2 for FEAT_STATE_CHECKED refactor(cpufeat): enable FEAT_TWED for FEAT_STATE_CHECKED refactor(cpufeat): enable FEAT_CSV2_2 for FEAT_STATE_CHECKED refactor(cpufeat): enable FEAT_ECV for FEAT_STATE_CHECKED refactor(cpufeat): enable FEAT_PAN for FEAT_STATE_CHECKED refactor(cpufeat): align FEAT_SB to new feature handling refactor(cpufeat): use alternative encoding for "SB" barrier refactor(cpufeat): enable SYS_REG_TRACE for FEAT_STATE_CHECKED fix(cpufeat): make stub enable functions "static inline" fix(mpam): feat_detect: support major/minor
| * | refactor(cpufeat): align FEAT_SEL2 to new feature handlingAndre Przywara2023-03-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | In ARMv8.4, the EL2 exception level got added to the secure world. Adapt and rename the existing is_armv8_4_sel2_present() function, to align its handling with the other CPU features. Change-Id: If11e1942fdeb63c63f36ab9e89be810347d1a952 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | refactor(cpufeat): enable FEAT_NV2 for FEAT_STATE_CHECKEDAndre Przywara2023-03-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we only support for FEAT_NV2 to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (CTX_INCLUDE_NEVE_REGS=2), by splitting get_armv8_4_feat_nv_support() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access the VNCR_EL2 system register. Also move the context saving code from assembly to C, and use the new is_feat_nv2_supported() function to guard its execution. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I85b080641995fb72cfd4ac933f7a3f75770c2cb9 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | refactor(cpufeat): enable FEAT_TWED for FEAT_STATE_CHECKEDAndre Przywara2023-03-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_TWED to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_FEAT_TWED=2), by splitting is_armv8_6_twed_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we set the trap delay time. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I58626230ef0af49886c0a197abace01e81f661d2 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | refactor(cpufeat): enable FEAT_CSV2_2 for FEAT_STATE_CHECKEDAndre Przywara2023-03-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_CSV2_2 to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_FEAT_CSV2_2=2), by splitting is_armv8_0_feat_csv2_2_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access the SCXTNUM_EL2 system register. Also move the context saving code from assembly to C, and use the new is_feat_csv2_2_supported() function to guard its execution. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I89c7bc883e6a65727fdbdd36eb3bfbffb2196da7 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | refactor(cpufeat): enable FEAT_ECV for FEAT_STATE_CHECKEDAndre Przywara2023-03-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_ECV to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_FEAT_ECV=2), by splitting is_feat_ecv_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access the CNTPOFF_EL2 system register. Also move the context saving code from assembly to C, and use the new is_feat_ecv_supported() function to guard its execution. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I4acd5384929f1902b62a87ae073aafa1472cd66b Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | refactor(cpufeat): enable FEAT_PAN for FEAT_STATE_CHECKEDAndre Przywara2023-03-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_PAN to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_FEAT_PAN=2), by splitting is_armv8_1_pan_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we PAN specific setup. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I58e5fe8d3c9332820391c7d93a8fb9dba4cf754a Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | refactor(cpufeat): enable SYS_REG_TRACE for FEAT_STATE_CHECKEDAndre Przywara2023-03-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we only support access to the trace unit by system registers (SYS_REG_TRACE) to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_SYS_REG_TRACE_FOR_NS=2), by adding is_feat_sys_reg_trace_supported(). That function considers both build time settings and runtime information (if needed), and is used before we access SYS_REG_TRACE related registers. The FVP platform decided to compile in support unconditionally (=1), even though this is an optional feature, so it is not available with the FVP model's default command line. Change that to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I450a574a4f6bd9fc269887037049c94c906f54b2 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | fix(fvp): unconditionally include lib/psa headersManish V Badarkhe2023-03-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Included lib/psa headers uncondiitionally to leverage their use across different FVP build configurations. Change-Id: I3417925e544d9ec20606a2ffba3d46ef7adaa730 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
* | | refactor(fvp): use RSS API to retrieve attestation token and keyManish V Badarkhe2023-03-223-135/+41
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | Retrieved the platform attestation token and delegated realm attestation key through the PSA delegated attestation layer. Even though FVP doesn't support RSS hardware today, it can still leverage the RSS implementation of these PSA interfaces in their mocking form (see PLAT_RSS_NOT_SUPPORTED). Therefore, platform APIs now call these PSA interfaces instead of directly providing these hardcoded values. Change-Id: I31d0ca58f6f1a444f513d954da4e3e67757321ad Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
* | Merge changes from topic "feat_state_part3" into integrationManish Pandey2023-03-202-3/+7
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: refactor(cpufeat): enable FEAT_VHE for FEAT_STATE_CHECKED refactor(mpam): enable FEAT_MPAM for FEAT_STATE_CHECKED feat(libc): add support for fallthrough statement refactor(spe): enable FEAT_SPE for FEAT_STATE_CHECKED refactor(cpufeat): rename ENABLE_SPE_FOR_LOWER_ELS to ENABLE_SPE_FOR_NS fix(spe): drop SPE EL2 context switch code
| * | refactor(cpufeat): enable FEAT_VHE for FEAT_STATE_CHECKEDAndre Przywara2023-03-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_VHE to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_FEAT_VHE=2), by splitting is_armv8_1_vhe_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access VHE related registers. Also move the context saving code from assembly to C, and use the new is_feat_vhe_supported() function to guard its execution. Enable VHE in its runtime detection version for all FVP builds. Change-Id: Ib397cd0c83e8c709bd6fed603560e39901fa672b Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | refactor(mpam): enable FEAT_MPAM for FEAT_STATE_CHECKEDAndre Przywara2023-03-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_MPAM to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_MPAM_FOR_LOWER_ELS=2), by splitting get_mpam_version() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access MPAM related registers. Also move the context saving code from assembly to C, and use the new is_feat_mpam_supported() function to guard its execution. ENABLE_MPAM_FOR_LOWER_ELS defaults to 0, so add a stub enable function to cover builds with compiler optimisations turned off. The unused mpam_enable() function call will normally be optimised away (because it would never be called), but with -O0 the compiler will leave the symbol in the object file. Change-Id: I531d87cb855a7c43471f861f625b5a6d4bc61313 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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