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* Merge changes from topics "plat_tests_scalability", "sb/tc-plat-tests" into ↵Sandrine Bailleux2023-05-165-38/+82
|\ | | | | | | | | | | | | | | | | | | | | integration * changes: test(tc): unify platform tests traces test(tc): return test failures count for tfm-testsuite test(tc): move platform tests in their own function test(tc): centralize platform error handling refactor(tc): define PLATFORM_TESTS for scale
| * test(tc): unify platform tests tracesSandrine Bailleux2023-05-151-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | Add some traces at the start and end of platform tests. These traces are the same regardless of the set of platform tests we run (NV counter tests / TF-M testsuite / future set of tests). This makes it easier to integrate these tests in the CI because we can now have a unified "expect" script for all platform tests, instead of having one dedicated "expect" script for each possible set of tests. Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Change-Id: I5ec30a7a25d8a9a4a90e3338a9789acff7ad4843
| * test(tc): return test failures count for tfm-testsuiteSandrine Bailleux2023-05-151-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | When running the "tfm-testsuite" set of platform tests, we now count the number of failed tests (in addition to printing a test summary) and report that back to the caller, i.e. tc_bl31_common_platform_setup(). This will be useful to consolidate the tests failure reporting code in a subsequent patch. Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Change-Id: I8e51f03869f3b2f264b6581b3bd2a53be0198057
| * test(tc): move platform tests in their own functionSandrine Bailleux2023-05-151-4/+11
| | | | | | | | | | | | | | | | | | | | This is a bit cleaner, as it avoids cluttering the normal boot execution path. It also gives us the opportunity to mark the tests function with the __dead2 attribute, which inform both the compiler and the developer that the test function never returns (since it suspends booting). Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Change-Id: I082a34a840ef791a2ac4c1f59b19b32aeb0a9ec7
| * test(tc): centralize platform error handlingSandrine Bailleux2023-05-154-15/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Note that this change only affects the platform tests execution path. It has no impact on the normal boot flow. Make individual test functions propagate an error code, instead of calling the platform error handler at the point of failure. The latter is now the responsibility of the caller - in this case tc_bl31_common_platform_setup(). Note that right now, tc_bl31_common_platform_setup() does not look at the said error code but this initial change opens up an opportunity to centralize any error handling in tc_bl31_common_platform_setup(), which we will seize in subsequent patches. Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Change-Id: Ib282b64039e0b1ec6e6d29476fbaa2bcd33cb0c7
| * refactor(tc): define PLATFORM_TESTS for scalelaurenw-arm2023-05-052-18/+22
| | | | | | | | | | | | | | | | | | For scalability when we add more tests in the future, add PLATFORM_TESTS macro when specific test flags, i.e. PLATFORM_TEST_NV_COUNTERS, are defined. Change-Id: Icb875a171dde673fca9fcf66624ac55383e7b641 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
* | Merge "fix(n1sdp): add platform-specific power domain functions" into ↵Manish Pandey2023-05-114-1/+49
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| * | fix(n1sdp): add platform-specific power domain functionsWerner Lewis2023-05-034-1/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 4d8c18196378824e388cf31ef991ba8fbbb09cbf added a redistributor power off to resolve an error on N1SDP/Morello. Prior to this fix, turning off both cores in a cluster would cause a hang when powering back on either core. This change introduced issues on other platforms with a different GIC implementation, and was reverted in commit 60719e4e0965aead49d927f12bf2a37bd2629012. This commit uses the previous fix in platform-specific implementations of power domain off/suspend functions. Signed-off-by: Werner Lewis <werner.lewis@arm.com> Change-Id: I52c463646c494fe931ff4ce47afb940a56978fcd
* | | Merge "fix(morello): add platform-specific power domain functions" into ↵Manish Pandey2023-05-114-0/+48
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| * | | fix(morello): add platform-specific power domain functionsWerner Lewis2023-05-034-0/+48
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 4d8c18196378824e388cf31ef991ba8fbbb09cbf added a redistributor power off to resolve an error on N1SDP/Morello. Prior to this fix, turning off both cores in a cluster would cause a hang when powering back on either core. This change introduced issues on other platforms with a different GIC implementation, and was reverted in commit 60719e4e0965aead49d927f12bf2a37bd2629012. This commit uses the previous fix in platform-specific implementations of power domain off/suspend functions. Signed-off-by: Werner Lewis <werner.lewis@arm.com> Change-Id: Ib7689a5e08ada3862406fa92019a6f0bcfb48d79
* | | Merge "fix(spmd): fix build error with spmd" into integrationMadhukar Pappireddy2023-05-113-6/+6
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| * | | fix(spmd): fix build error with spmdGovindraj Raja2023-05-103-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently when we build with 'SPD=spmd SPMD_SPM_AT_SEL2=0' options, this causes a build failure as 'plat_spmd_handle_group0_interrupt' is called irrespective of 'SPMD_SPM_AT_SEL2' usage in 'spmd_group0_interrupt_handler_nwd' So make 'plat_spmd_handle_group0_interrupt' dummy implementation available just when spmd is enabled and SPMC_AT_EL3 is disabled. Change-Id: Iaccd38faab81671c98f9165f318145187dca9bc2 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
* | | | build(fpga): reduce cpu_libs to tc and neoverseDaniel Boulby2023-05-101-18/+14
|/ / / | | | | | | | | | | | | Change-Id: I20e88d5e712dafa7364b7932b8b4aaa9051bea55 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
* | | Merge changes I1bfa797e,I0ec7a70e into integrationManish Pandey2023-05-092-2/+2
|\ \ \ | | | | | | | | | | | | | | | | | | | | * changes: fix(tree): correct some typos fix(rockchip): use semicolon instead of comma
| * | | fix(tree): correct some typosElyes Haouas2023-05-092-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | found using codespell (https://github.com/codespell-project/codespell). Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373
* | | | Merge changes from topic "mp/feat_ras" into integrationManish Pandey2023-05-098-10/+15
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | * changes: refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED refactor(ras): replace RAS_EXTENSION with FEAT_RAS
| * | | | refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKEDAndre Przywara2023-05-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_RAS to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (FEAT_RAS=2), by splitting is_armv8_2_feat_ras_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access RAS related registers. Also move the context saving code from assembly to C, and use the new is_feat_ras_supported() function to guard its execution. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I30498f72fd80b136850856244687400456a03d0e Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
| * | | | refactor(ras): replace RAS_EXTENSION with FEAT_RASManish Pandey2023-05-098-10/+14
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current usage of RAS_EXTENSION in TF-A codebase is to cater for two things in TF-A : 1. Pull in necessary framework and platform hooks for Firmware first handling(FFH) of RAS errors. 2. Manage the FEAT_RAS extension when switching the worlds. FFH means that all the EAs from NS are trapped in EL3 first and signaled to NS world later after the first handling is done in firmware. There is an alternate way of handling RAS errors viz Kernel First handling(KFH). Tying FEAT_RAS to RAS_EXTENSION build flag was not correct as the feature is needed for proper handling KFH in as well. This patch breaks down the RAS_EXTENSION flag into a flag to denote the CPU architecture `ENABLE_FEAT_RAS` which is used in context management during world switch and another flag `RAS_FFH_SUPPORT` to pull in required framework and platform hooks for FFH. Proper support for KFH will be added in future patches. BREAKING CHANGE: The previous RAS_EXTENSION is now deprecated. The equivalent functionality can be achieved by the following 2 options: - ENABLE_FEAT_RAS - RAS_FFH_SUPPORT Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I1abb9ab6622b8f1b15712b12f17612804d48a6ec
* | | | Merge changes from topic "srm/Errata_ABI_El3" into integrationMadhukar Pappireddy2023-05-092-0/+65
|\ \ \ \ | |/ / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: docs(errata_abi): document the errata abi changes feat(fvp): enable errata management interface fix(cpus): workaround platforms non-arm interconnect refactor(errata_abi): factor in non-arm interconnect feat(errata_abi): errata management firmware interface
| * | | feat(fvp): enable errata management interfaceSona Mathew2023-05-052-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Errata ABI feature specific build flag, flag to enable CPUs in the cpu list, flags to test non-arm interconnect based errata flags when enabled from a platform level. Added to the FVP platform makefile to test the errata abi feature implementation. The flags to enable CPUs in the cpu list will be removed once synchronized with the errata framework. Change-Id: I30877a22ac1348906a6ddfb26f9e8839912d3572 Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
* | | | Merge changes from topic "assert_boolean_set" into integrationManish Pandey2023-05-091-0/+2
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: build!: check boolean flags are not empty fix(build): add a default value for INVERTED_MEMMAP fix(a5ds): add default value for ARM_DISABLE_TRUSTED_WDOG fix(st-crypto): move flag control into source code fix(stm32mp1): always define PKA algos flags fix(stm32mp1): remove boolean check on PLAT_TBBR_IMG_DEF
| * | | | fix(a5ds): add default value for ARM_DISABLE_TRUSTED_WDOGManish Pandey2023-05-031-0/+2
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | With introduction of check on boolean flags, it should be ensured that each boolean flag has default value provided by platform. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ia92c3dded842e14099b4a7667569605d7066a8f9
* | | | Merge "feat(fvp): introduce PLATFORM_TEST_RAS_FFH config" into integrationManish Pandey2023-05-093-3/+72
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| * | | feat(fvp): introduce PLATFORM_TEST_RAS_FFH configManish Pandey2023-05-043-3/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While doing RAS related tests there were few patches related with fault injection and handling were applied through CI hooks. These patches were invisible as they were applied and removed after the build is done. This patch introduces build macro PLATFORM_TEST_RAS_FFH and moves the patches applied through CI under this. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Iddba52f3ebf21f575a473e50c607a944391156b9
* | | | feat(tc): allow secure watchdog timer to trigger periodicallyMadhukar Pappireddy2023-05-045-9/+56
| |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch does the following: 1. Configures SBSA secure watchdog timer as Group0 interrupt for TC platform while keeping it as Group1 secure interrupt for other CSS based SoCs. 2. Programs the watchdog timer to trigger periodically 3. Provides a Group0 interrupt handler for TC platform port to deactivate the EL3 interrupt due to expiry of secure watchdog timer and refresh it explicitly. Change-Id: I3847d6eb7347c6ea0e527b97b096119ca1e6701b Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | | Merge "feat(fvp): define ns memory in the SPMC manifest" into integrationMadhukar Pappireddy2023-05-042-9/+24
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| * | feat(fvp): define ns memory in the SPMC manifestJ-Alves2023-05-032-9/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPMC (Hafnium) looks for secure and non-secure ranges in its manifest. Those relate with ranges that can be used by SPs in their FF-A manifests. The NS memory that is not used by SPs will be assigned to the NWd, for it to share memory with SPs as needed. Thus, this limits the memory the NWd can share with SPs, to prevent NWD VMs from sharing memory that belongs to other critical components. Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: Iad03eb138a57068fbb18c53141bdf6bf9c171b28
* | | Merge "fix(tc): only suspend booting after running plat tests" into integrationSandrine Bailleux2023-05-041-1/+3
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| * | | fix(tc): only suspend booting after running plat testslaurenw-arm2023-05-041-1/+3
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. When doing a normal boot, tc_bl31_common_platform_setup() should simply configure the platform and return. 2. When we are running the platform tests instead, tc_bl31_common_platform_setup() should run the tests then suspend booting (and thus never return). We were incorreclty suspending the boot in case 1 as well. Put that code under a preprocessor condition (PLATFORM_TEST_NV_COUNTERS or PLATFORM_TEST_TFM_TESTSUITE) to fix this. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I7d20800e3bcd85261e2cdad325586d184e12a3e3
* | | Merge changes from topic "mp/group0_support" into integrationOlivier Deprez2023-05-035-0/+51
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | * changes: docs(spm): support for handling Group0 interrupts feat(spmd): introduce platform handler for Group0 interrupt feat(spmd): add support for FFA_EL3_INTR_HANDLE_32 ABI feat(spmd): register handler for group0 interrupt from NWd
| * | feat(spmd): introduce platform handler for Group0 interruptMadhukar Pappireddy2023-05-015-0/+51
| |/ | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a handler for FVP platform to triage Group0 secure interrupts. Currently, it is empty but serves as a placeholder for future Group0 interrupt sources. Moreover, this patch also provides a dummy implementation of the above mentioned platform hook for QEMU, corstone100, n1sdp and hikey960 ports. Change-Id: I01d3451408f47ac313b0af74046cce89f89b85bb Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | Merge "build: deprecate Arm rde1edge" into integrationManish V Badarkhe2023-05-021-1/+4
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| * | build: deprecate Arm rde1edgeManish V Badarkhe2023-04-201-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Arm has decided to deprecate the rde1edge platform. The development of software and fast model for this platform have been discontinued. Hence, updated the makefile to warn about the deprecation of this platform, and also reflected it in the documentation. Change-Id: I0d44de4590dd5dce02c7c4b433df25dc438e6c49 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
* | | Merge "fix(sme): disable SME for SPD=spmd" into integrationManish Pandey2023-05-021-1/+3
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| * | | fix(sme): disable SME for SPD=spmdJayanth Dodderi Chidanand2023-04-281-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPMD is not compatible with ENABLE_SME_FOR_NS. Hence disable SME when SPD=spmd Change-Id: I8bcf2493819718732563f9db69f7186ac7437637 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* | | | Merge changes Ia1142b31,I424f1cde into integrationSandrine Bailleux2023-05-025-10/+10
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | * changes: fix(tc): enable the execution of both platform tests fix(tc): update the name of mbedtls config header
| * | | | fix(tc): enable the execution of both platform testsTamas Ban2023-04-274-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The C preprocessor cannot compare defines against strings. Such an expression is always evaluated to be true. Therefore, its usage in a conditional expression results that always the first branch is taken. Other branches cannot be reached by any configuration value. The fix removes this string comparison and instead it introduces distinct defines for all the cases. Signed-off-by: Tamas Ban <tamas.ban@arm.com> Change-Id: Ia1142b31b6778686c74e1e882fe4604fe3b6501d
| * | | | fix(tc): update the name of mbedtls config headerTamas Ban2023-04-271-2/+2
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recently mbedtls_cofig.h was renamed to: - mbedtls_config-2.h - mbedtls_config-3.h Modify the include order to resolve the static check failure in the CI. Signed-off-by: Tamas Ban <tamas.ban@arm.com> Change-Id: I424f1cde199397b8df780a9514f1042e601c6502
* | | | Merge "refactor(fiptool): move plat_fiptool.mk to tools" into integrationSandrine Bailleux2023-05-023-97/+0
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| * | | refactor(fiptool): move plat_fiptool.mk to toolsRaef Coles2023-02-063-98/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move all plat_fiptool.mks into tools, change the logic to recursively check for tools/fiptool/plat_fiptool/<plat_path>/plat_fiptool.mk I.e. for a platform that has the path "plat/arm/board/tc/platform.mk", the makefile will now load the first existing file from: - tools/fiptool/plat_fiptool/arm/board/tc/plat_fiptool.mk - tools/fiptool/plat_fiptool/arm/board/plat_fiptool.mk - tools/fiptool/plat_fiptool/arm/plat_fiptool.mk This enables fiptool to support multiple platforms, or a specific one. Remove file-copying previously being used to handle old default path. Remove custom file cleaning in plat_fiptool.mk. Change-Id: I95245bcf7143b329481d4394ab64f29bfe9de5ab Signed-off-by: Raef Coles <raef.coles@arm.com>
* | | | Merge "feat(fvp): introduce PLATFORM_TEST_EA_FFH config" into integrationManish Pandey2023-04-282-0/+62
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| * | | | feat(fvp): introduce PLATFORM_TEST_EA_FFH configManish Pandey2023-04-282-0/+62
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FVP currently does not have proper handler to do Firmware First Handling (FFH) of lower EL External aborts and it ends up in EL3 panic. To test the scenarios sensibly we need a proper handling when the FVP is under test so that we do not change the default behavior. Introduce PLATFORM_TEST_EA_FFH config which will be enabled in CI scripts and implement a proper handling for Sync EA and SErrors from lower EL. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ib130154206b17f72c49c9f07de2d92f35a97ab0b
* | | | Merge "feat(sme): enable SME2 functionality for NS world" into integrationManish Pandey2023-04-281-0/+1
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| * | | | feat(sme): enable SME2 functionality for NS worldJayanth Dodderi Chidanand2023-04-271-0/+1
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FEAT_SME2 is an extension of FEAT_SME and an optional feature from v9.2. Its an extension of SME, wherein it not only processes matrix operations efficiently, but also provides outer-product instructions to accelerate matrix operations. It affords instructions for multi-vector operations. Further, it adds an 512 bit architectural register ZT0. This patch implements all the changes introduced with FEAT_SME2 to ensure that the instructions are allowed to access ZT0 register from Non-secure lower exception levels. Additionally, it adds support to ensure FEAT_SME2 is aligned with the existing FEATURE DETECTION mechanism, and documented. Change-Id: Iee0f61943304a9cfc3db8f986047b1321d0a6463 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* | | | build(fvp): reduce the number of cpu libraries included by defaultBoyan Karatotev2023-04-261-18/+8
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fvp build includes a very large number of cpus so that it can run on a wide range of models. One config (HW_ASSISTED_COHERENCY=1 CTX_INCLUDE_AARCH32_REGS=0) includes an unusually large number of cpus. Well, the list is quite arbitrary and incomplete. As we're currently out of BL31 space on the fvp, remove all that are not routinely run in the CI to buy us some time. Also use the opportunity to reorder the list into something searchable. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I8c6cad41327451edf0d3a0e92c43d6c72c254aac
* | | Merge "refactor(cpufeat): enable FEAT_DIT for FEAT_STATE_CHECKED" into ↵Manish Pandey2023-04-251-0/+1
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| * | | refactor(cpufeat): enable FEAT_DIT for FEAT_STATE_CHECKEDAndre Przywara2023-04-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_DIT to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_DIT=2), by splitting is_armv8_4_dit_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed). We use ENABLE_DIT in two occassions in assembly code, where we just set the DIT bit in the DIT system register. Protect those two cases by reading the CPU ID register when ENABLE_DIT is set to 2. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I506d352f18e23c60db8cdf08edb449f60adbe098 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | | Merge "refactor(morello): remove duplication of platform information struct" ↵Manish V Badarkhe2023-04-254-103/+38
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| * | | refactor(morello): remove duplication of platform information structWerner Lewis2023-04-194-103/+38
| | |/ | |/| | | | | | | | | | | | | | | | | | | morello_plat_info is defined identically in multiple files, definition is moved to a header file to avoid duplication. Signed-off-by: Werner Lewis <werner.lewis@arm.com> Change-Id: I607354902c55f5c31f0732de9db60604b82aef97
* | | Merge "feat(gcs): support guarded control stack" into integrationBipin Ravi2023-04-251-0/+1
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