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| author | Manish Pandey <manish.pandey2@arm.com> | 2023-05-16 16:58:09 +0200 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2023-05-16 16:58:09 +0200 |
| commit | 2834bc6b83d94a50c82ebedd65288aa15678094a (patch) | |
| tree | 7749edf86823967b3e4c2cdaa3b432f2c5789efc | |
| parent | 20304ce22f26eab17eb5d02e7de4911beff6b994 (diff) | |
| parent | cb6c8efc4f2dd951b2b51801a12ba1755d49fe79 (diff) | |
| download | arm-trusted-firmware-2834bc6b83d94a50c82ebedd65288aa15678094a.tar.gz | |
Merge "fix(tegra210): mark bits [23:17] as zero for Fast SMCs" into integration
| -rw-r--r-- | plat/nvidia/tegra/soc/t210/plat_sip_calls.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/plat/nvidia/tegra/soc/t210/plat_sip_calls.c b/plat/nvidia/tegra/soc/t210/plat_sip_calls.c index 93d12832e..f3ebd4bb9 100644 --- a/plat/nvidia/tegra/soc/t210/plat_sip_calls.c +++ b/plat/nvidia/tegra/soc/t210/plat_sip_calls.c @@ -33,8 +33,7 @@ /******************************************************************************* * Tegra210 SiP SMCs ******************************************************************************/ -#define TEGRA_SIP_PMC_COMMANDS_LEGACY U(0xC2FEFE00) -#define TEGRA_SIP_PMC_COMMANDS U(0xC2FFFE00) +#define TEGRA_SIP_PMC_COMMANDS U(0xC200FE00) /******************************************************************************* * This function is responsible for handling all T210 SiP calls @@ -55,10 +54,12 @@ int plat_sip_handler(uint32_t smc_fid, if (!ns) SMC_RET1(handle, SMC_UNK); - if ((smc_fid == TEGRA_SIP_PMC_COMMANDS) || (smc_fid == TEGRA_SIP_PMC_COMMANDS_LEGACY)) { + if (smc_fid == TEGRA_SIP_PMC_COMMANDS) { + /* check the address is within PMC range and is 4byte aligned */ - if ((x2 >= TEGRA_PMC_SIZE) || (x2 & 0x3)) + if ((x2 >= TEGRA_PMC_SIZE) || (x2 & 0x3)) { return -EINVAL; + } switch (x2) { /* Black listed PMC registers */ |