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* Merge "build(fpga): reduce cpu_libs to tc and neoverse" into integrationManish V Badarkhe2023-05-101-18/+14
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| * build(fpga): reduce cpu_libs to tc and neoverseDaniel Boulby2023-05-101-18/+14
| | | | | | | | | | Change-Id: I20e88d5e712dafa7364b7932b8b4aaa9051bea55 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
* | Merge "docs: update release and code freeze dates" into integrationJoanna Farley2023-05-101-1/+3
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| * | docs: update release and code freeze datesHarrison Mutai2023-05-051-1/+3
| | | | | | | | | | | | | | | Signed-off-by: Harrison Mutai <harrison.mutai@arm.com> Change-Id: If782bd337d10213cb74503f4ea54ed304d6e4c34
* | | Merge "fix(pmu): unconditionally save PMCR_EL0" into integrationManish Pandey2023-05-104-78/+7
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| * | fix(pmu): unconditionally save PMCR_EL0Boyan Karatotev2023-05-054-78/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reading back a RES0 bit does not necessarily mean it will be read as 0. The Arm ARM explicitly warns against doing this. The PMU initialisation code tries to set such bits to 1 (in MDCR_EL3) regardless of whether they are in use or are RES0, checking their value could be wrong and PMCR_EL0 might not end up being saved. Save PMCR_EL0 unconditionally to prevent this. Remove the security state change as the outgoing state is not relevant to what the root world context should look like. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: Id43667d37b0e2da3ded0beaf23fa0d4f9013f470
* | | Merge changes I5bb43cb0,I6aebe2ca,Ib59df16a,I9d037ab2,I9df5a465, ... into ↵Manish V Badarkhe2023-05-097-28/+50
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | integration * changes: fix(msm8916): add timeout for crash console TX flush style(msm8916): use size macros feat(msm8916): expose more timer frames fix(msm8916): drop unneeded initialization of CNTACR build(msm8916): disable unneeded workarounds fix(msm8916): flush dcache after writing msm8916_entry_point fix(msm8916): print \r before \n on UART console
| * | | fix(msm8916): add timeout for crash console TX flushStephan Gerhold2023-05-092-14/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Resetting the UART DM controller while there are still remaining characters in the FIFO often results in corruption on the UART receiver side. To avoid this the msm8916 crash console implementation tries to wait until the TX FIFO is empty. Unfortunately this might spin forever if the transmitter was disabled before it has fully finished transmitting. In this case the TXEMT bit console_uartdm_core_flush is waiting for will never get set. There seems to be no good way to detect if the transmitter is actually enabled via the status registers. However, the TX FIFO is fairly small and should not take too long to get flushed, so fix this by simply limiting the amount of iterations with a short timeout. Move the code to console_uartdm_core_init to ensure that this always happens before resetting the transmitter (also during initialization). Change-Id: I5bb43cb0b6c029bcd15e253d60d36c0b310e108b Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
| * | | style(msm8916): use size macrosStephan Gerhold2023-05-092-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the pre-defined size macros (SZ_*) for more clarity and to avoid having to add comments to each size represented by hexadecimal numbers. Change-Id: I6aebe2caf1365279670955b9b507dec7d7b04457 Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
| * | | feat(msm8916): expose more timer framesStephan Gerhold2023-05-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The memory-mapped generic timer on msm8916 has 7 timer frames, but currently only one is exposed for usage in the non-secure world. The platform port is currently only designed to be used as minimal PSCI implementation, without secure world that could make use of the other timer frames. Let's make all of them available to the normal world. If needed this could still be changed later by reserving some timer frames conditionally to a specific SPD being enabled in the build. Change-Id: Ib59df16aa1fd3dbc875ab6369c133737830c98c6 Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
| * | | fix(msm8916): drop unneeded initialization of CNTACRStephan Gerhold2023-05-091-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Normal world software is responsible to initialize CNTACR as needed. There is no existing software for msm8916 that depends on having this initialization in BL31 so drop it before anything starts to rely on it. Related issue: https://github.com/ARM-software/tf-issues/issues/170 Change-Id: I9d037ab218c0c1c8a5d5523722013eba531f4728 Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
| * | | build(msm8916): disable unneeded workaroundsStephan Gerhold2023-05-091-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Cortex-A53 cores used in the msm8916 platform are not affected by CVE-2017-5715 and CVE-2022-23960, so disable the workarounds for them to drop the unused code from the compiled binary. Change-Id: I9df5a4657c4fd90702b4db4e82d4ee1a2f60303c Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
| * | | fix(msm8916): flush dcache after writing msm8916_entry_pointStephan Gerhold2023-05-091-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | msm8916_entry_point is read with caches off (and even from two different physical addresses when read through the "boot remapper"), so it should be flushed to RAM after writing it. Change-Id: I5c8193954bb28043b0a46fb2038f629bd8796c74 Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
| * | | fix(msm8916): print \r before \n on UART consoleStephan Gerhold2023-05-091-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UART drivers in TF-A are expected to print \r before \n. Some terminal emulators expect \r\n as line endings by default so not doing this causes broken line breaks. Change-Id: I271a35a7c6907441bc71713b0b6a1da19da96878 Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
* | | | Merge changes I1bfa797e,I0ec7a70e into integrationManish Pandey2023-05-09110-137/+137
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | * changes: fix(tree): correct some typos fix(rockchip): use semicolon instead of comma
| * | | | fix(tree): correct some typosElyes Haouas2023-05-09109-136/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | found using codespell (https://github.com/codespell-project/codespell). Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373
| * | | | fix(rockchip): use semicolon instead of commaElyes Haouas2023-05-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use semicolon insted of comma at the end of line. Change-Id: I0ec7a70ec659333c98d586f7bebd5d91bd6c6cc1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
* | | | | Merge changes from topic "mp/feat_ras" into integrationManish Pandey2023-05-0930-137/+177
|\ \ \ \ \ | |_|/ / / |/| | | | | | | | | | | | | | | | | | | * changes: refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED refactor(ras): replace RAS_EXTENSION with FEAT_RAS
| * | | | refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKEDAndre Przywara2023-05-099-59/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_RAS to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (FEAT_RAS=2), by splitting is_armv8_2_feat_ras_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access RAS related registers. Also move the context saving code from assembly to C, and use the new is_feat_ras_supported() function to guard its execution. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I30498f72fd80b136850856244687400456a03d0e Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
| * | | | refactor(ras): replace RAS_EXTENSION with FEAT_RASManish Pandey2023-05-0927-90/+145
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current usage of RAS_EXTENSION in TF-A codebase is to cater for two things in TF-A : 1. Pull in necessary framework and platform hooks for Firmware first handling(FFH) of RAS errors. 2. Manage the FEAT_RAS extension when switching the worlds. FFH means that all the EAs from NS are trapped in EL3 first and signaled to NS world later after the first handling is done in firmware. There is an alternate way of handling RAS errors viz Kernel First handling(KFH). Tying FEAT_RAS to RAS_EXTENSION build flag was not correct as the feature is needed for proper handling KFH in as well. This patch breaks down the RAS_EXTENSION flag into a flag to denote the CPU architecture `ENABLE_FEAT_RAS` which is used in context management during world switch and another flag `RAS_FFH_SUPPORT` to pull in required framework and platform hooks for FFH. Proper support for KFH will be added in future patches. BREAKING CHANGE: The previous RAS_EXTENSION is now deprecated. The equivalent functionality can be achieved by the following 2 options: - ENABLE_FEAT_RAS - RAS_FFH_SUPPORT Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I1abb9ab6622b8f1b15712b12f17612804d48a6ec
* | | | Merge changes from topic "srm/Errata_ABI_El3" into integrationMadhukar Pappireddy2023-05-0917-2/+891
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: docs(errata_abi): document the errata abi changes feat(fvp): enable errata management interface fix(cpus): workaround platforms non-arm interconnect refactor(errata_abi): factor in non-arm interconnect feat(errata_abi): errata management firmware interface
| * | | | docs(errata_abi): document the errata abi changesSona Mathew2023-05-053-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updated errata ABI feature enable flag and the errata non-arm interconnect based flag, the default values for when the feature is not enabled. Change-Id: Ieb2144a1bc38f4ed684fda8280842a18964ba148 Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
| * | | | feat(fvp): enable errata management interfaceSona Mathew2023-05-052-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Errata ABI feature specific build flag, flag to enable CPUs in the cpu list, flags to test non-arm interconnect based errata flags when enabled from a platform level. Added to the FVP platform makefile to test the errata abi feature implementation. The flags to enable CPUs in the cpu list will be removed once synchronized with the errata framework. Change-Id: I30877a22ac1348906a6ddfb26f9e8839912d3572 Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
| * | | | fix(cpus): workaround platforms non-arm interconnectSona Mathew2023-05-054-19/+147
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The workarounds for these below mentioned errata are not implemented in EL3, but the flags can be enabled/disabled at a platform level based on arm/non-arm interconnect IP. The ABI helps assist the Kernel in the process of mitigation for the following errata: Cortex-A715: erratum 2701951 Neoverse V2: erratum 2719103 Cortex-A710: erratum 2701952 Cortex-X2: erratum 2701952 Neoverse N2: erratum 2728475 Neoverse V1: erratum 2701953 Cortex-A78: erratum 2712571 Cortex-A78AE: erratum 2712574 Cortex-A78C: erratum 2712575 EL3 provides an appropriate return value via errata ABI when the kernel makes an SMC call using the EM_CPU_ERRATUM_FEATURES FID with the appropriate erratum ID. Change-Id: I35bd69d812dba37410dd8bc2bbde20d4955b0850 Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
| * | | | refactor(errata_abi): factor in non-arm interconnectSona Mathew2023-05-054-12/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Workaround to help enable the kernel to query errata status using the errata abi feature for platforms with a non-arm interconnect. Change-Id: I47b03eaee5a0a763056ae71883fa30dfacb9b3f7 Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
| * | | | feat(errata_abi): errata management firmware interfaceSona Mathew2023-05-0510-2/+669
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the errata management firmware interface for lower ELs to discover details about CPU erratum. Based on the CPU erratum identifier the interface enables the OS to find the mitigation of an erratum in EL3. The ABI can only be present in a system that is compliant with SMCCCv1.1 or higher. This implements v1.0 of the errata ABI spec. For details on all possible return values, refer the design documentation below: ABI design documentation: https://developer.arm.com/documentation/den0100/1-0?lang=en Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com> Change-Id: I70f0e2569cf92e6e02ad82e3e77874546232b89a
* | | | | Merge "fix(qemu-sbsa): enable FGT" into integrationBipin Ravi2023-05-091-0/+3
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| * | | | | fix(qemu-sbsa): enable FGTMarcin Juszkiewicz2023-04-281-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QEMU 7.2+ has FEAT_FGT support added to 'max' cpu. So let's enable it to make Debian 'bookworm' kernel boot on sbsa-ref/max setup. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Change-Id: I49fb3e742b69ce7be5666e0144525dde21a68238
* | | | | | Merge changes from topic "bk/context_refactor" into integrationManish V Badarkhe2023-05-097-47/+44
|\ \ \ \ \ \ | | |_|_|/ / | |/| | | | | | | | | | | | | | | | | | | | | | * changes: fix(gicv3): restore scr_el3 after changing it refactor(cm): make SVE and SME build dependencies logical
| * | | | | fix(gicv3): restore scr_el3 after changing itBoyan Karatotev2023-05-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EL3's context is poorly defined as it is and polluting it further is not a good idea. Put it back as it was before the function call. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I9d13c9517962b501246989fd2126d08410191784
| * | | | | refactor(cm): make SVE and SME build dependencies logicalBoyan Karatotev2023-05-056-47/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, enabling SME forces SVE off. However, the SME enablement requires SVE to be enabled, which is reflected in code. This is the opposite of what the build flags require. Further, the few platforms that enable SME also explicitly enable SVE. Their platform.mk runs after the defaults.mk file so this override never materializes. As a result, the override is only present on the commandline. Change it to something sensible where if SME is on then code can rely on SVE being on too. Do this with a check in the Makefile as it is the more widely used pattern. This maintains all valid use cases but subtly changes corner cases no one uses at the moment to require a slightly different combination of flags. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: If7ca3972ebc3c321e554533d7bc81af49c2472be
* | | | | | Merge "docs: update TZC secured DRAM map for FVP and Juno" into integrationMadhukar Pappireddy2023-05-091-4/+34
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| * | | | | | docs: update TZC secured DRAM map for FVP and JunoManish V Badarkhe2023-05-081-4/+34
| | |_|/ / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updated the documentation to include missing details about the TZC secured DRAM mapping for the FVP and Juno platforms. Change-Id: I10e59b9f9686fa2fef97f89864ebc272b10e5c0b Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
* | | | | | Merge changes I06b35f11,If80573d6 into integrationManish Pandey2023-05-094-171/+1
|\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: docs: remove plat_convert_pk() interface from release doc chore(io): remove io_dummy driver
| * | | | | | docs: remove plat_convert_pk() interface from release docSandrine Bailleux2023-04-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code was already removed as part of commit 4ac5b3949d87 "refactor(auth): replace plat_convert_pk". The present commit just removes it from the release documentation. Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Change-Id: I06b35f110c844267d69a865df55dd451ed2f08cd
| * | | | | | chore(io): remove io_dummy driverSandrine Bailleux2023-04-284-170/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In accordance with [1], delete the io_dummy driver code in preparation for the v2.9 release. [1] https://trustedfirmware-a.readthedocs.io/en/latest/about/release-information.html Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Change-Id: If80573d6f889624ef06b099fd267ee85f3a6331e
* | | | | | | Merge "feat(mt8188): add MT8188 SPM debug logs" into integrationManish Pandey2023-05-098-11/+86
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| * | | | | | feat(mt8188): add MT8188 SPM debug logsJason Chen2023-05-088-11/+86
| | |/ / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add debug logs for tracking the status of suspend and resume. Change-Id: Id2d2ab06fadb3118ab66f816937e0dd6e43dbdc3 Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com>
* | | | | | Merge changes from topic "assert_boolean_set" into integrationManish Pandey2023-05-096-17/+15
|\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: build!: check boolean flags are not empty fix(build): add a default value for INVERTED_MEMMAP fix(a5ds): add default value for ARM_DISABLE_TRUSTED_WDOG fix(st-crypto): move flag control into source code fix(stm32mp1): always define PKA algos flags fix(stm32mp1): remove boolean check on PLAT_TBBR_IMG_DEF
| * | | | | | build!: check boolean flags are not emptyYann Gautier2023-05-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For numeric flags, there is a check for the value to be set. Do the same for boolean flags. This avoids issues where a flag is defined but without a value, leading to potential unexpected behaviors. Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: Ib00da2784339471058887e93434d96ccba2aebb2
| * | | | | | fix(build): add a default value for INVERTED_MEMMAPYann Gautier2023-05-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is needed to check the validity of boolean flags with the updated macro assert_boolean. Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I185beb55606a4ca435d2fee2092fc61725859aa1
| * | | | | | fix(a5ds): add default value for ARM_DISABLE_TRUSTED_WDOGManish Pandey2023-05-031-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With introduction of check on boolean flags, it should be ensured that each boolean flag has default value provided by platform. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ia92c3dded842e14099b4a7667569605d7066a8f9
| * | | | | | fix(st-crypto): move flag control into source codeLionel Debieve2023-05-032-15/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the control from the include file to avoid compilation issue. Add the check in the source code instead. Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com> Change-Id: I533f829607f76389399a3e8dbc3c6095278562ab
| * | | | | | fix(stm32mp1): always define PKA algos flagsYann Gautier2023-05-031-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The flags to set PKA algo are set to 0 when TRUSTED_BOARD_BOOT is not set. Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: Ib70a2bc51451a2047d7a50a8307e9063d4a2a0ee
| * | | | | | fix(stm32mp1): remove boolean check on PLAT_TBBR_IMG_DEFYann Gautier2023-05-031-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This flag just needs to be defined, and does not need to have a boolean value. Remove it from the assert_booleans check. Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: I4e4c9ae1e5003ca2cf7c0c0e31d1561d032937c8
* | | | | | | Merge changes from topics "gr/gcc12", "jc/toolchain_update_2.9" into integrationManish Pandey2023-05-093-1/+11
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: docs(build): update GCC to 12.2.Rel1 version fix(build): allow lower address access with gcc-12
| * | | | | | | docs(build): update GCC to 12.2.Rel1 versionJayanth Dodderi Chidanand2023-05-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updating toolchain to the latest production release version 12.2.Rel1 publicly available on https://developer.arm.com/ We build TF-A in CI using: AArch32 bare-metal target (arm-none-eabi) AArch64 ELF bare-metal target (aarch64-none-elf) Change-Id: Ib603cf7417e6878683a1100d5f55311188e36e8e Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
| * | | | | | | fix(build): allow lower address access with gcc-12Govindraj Raja2023-05-092-0/+10
|/ / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With gcc-12 any lower address access can trigger a warning/error this would be useful in other parts of system but in TF-A there are various reasons to access to the lower address ranges, example using mmio_read_*/writes_* So setup to allow access to lower addresses while using gcc-12 Change-Id: Id1b4012b13bc6876d83b90a347fee12478a1921d Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
* | | | | | | Merge "feat(fvp): introduce PLATFORM_TEST_RAS_FFH config" into integrationManish Pandey2023-05-093-3/+72
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| * | | | | | feat(fvp): introduce PLATFORM_TEST_RAS_FFH configManish Pandey2023-05-043-3/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While doing RAS related tests there were few patches related with fault injection and handling were applied through CI hooks. These patches were invisible as they were applied and removed after the build is done. This patch introduces build macro PLATFORM_TEST_RAS_FFH and moves the patches applied through CI under this. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Iddba52f3ebf21f575a473e50c607a944391156b9
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