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path: root/opcodes/riscv-dis.c
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* RISC-V: Allow instruction require more than one extensionJim Wilson2018-08-301-1/+1
* RISC-V: Set insn info fields correctly when disassembling.Jim Wilson2018-07-301-0/+26
* opcodes error messagesAlan Modra2018-03-031-2/+2
* RISC-V: Disassemble x0 based addresses as 0.Jim Wilson2018-01-091-1/+1
* RISC-V: Print symbol address for jalr w/ zero offset.Jim Wilson2018-01-051-0/+2
* Update year range in copyright notice of binutils filesAlan Modra2018-01-031-1/+1
* Fix typos in error and option messages in OPCODES library.Nick Clifton2017-07-251-1/+1
* Move print_insn_XXX to an opcodes internal headerYao Qi2017-05-241-1/+1
* RISC-V: Fix disassemble for c.li, c.andi and c.addiwKito Cheng2017-05-041-0/+1
* RISC-V: Resurrect GP-relative disassembly hintsPalmer Dabbelt2017-04-041-1/+1
* Add fall through comment.Dilyan Palauzov2017-01-031-0/+1
* Update year range in copyright notice of all files.Alan Modra2017-01-021-1/+1
* Re-work RISC-V gas flags: now we just support -mabi and -marchAndrew Waterman2016-12-201-2/+6
* Add support for RISC-V architecture.Nick Clifton2016-11-011-0/+502
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