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| author | Jim Wilson <jimw@sifive.com> | 2018-07-30 13:55:41 -0700 |
|---|---|---|
| committer | Jim Wilson <jimw@sifive.com> | 2018-07-30 13:55:41 -0700 |
| commit | eb41b24898e9858852c98f9275e7a4adee860d7b (patch) | |
| tree | 67d79ae29e20d2f353e58a370ec84499b3d9e9f4 /opcodes/riscv-dis.c | |
| parent | c8f2dc0dc967222673d71a0493958a587c53ae3c (diff) | |
| download | binutils-gdb-eb41b24898e9858852c98f9275e7a4adee860d7b.tar.gz | |
RISC-V: Set insn info fields correctly when disassembling.
include/
* opcode/riscv.h (INSN_TYPE, INSN_BRANCH, INSN_CONDBRANCH, INSN_JSR)
(INSN_DREF, INSN_DATA_SIZE, INSN_DATA_SIZE_SHIFT, INSN_1_BYTE)
(INSN_2_BYTE, INSN_4_BYTE, INSN_8_BYTE, INSN_16_BYTE): New.
opcodes/
* riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
fields.
* riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
Diffstat (limited to 'opcodes/riscv-dis.c')
| -rw-r--r-- | opcodes/riscv-dis.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index e8fc6ea3326..5b29d62a8c4 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -446,6 +446,32 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) pd->print_addr = -1; } + /* Finish filling out insn_info fields. */ + switch (op->pinfo & INSN_TYPE) + { + case INSN_BRANCH: + info->insn_type = dis_branch; + break; + case INSN_CONDBRANCH: + info->insn_type = dis_condbranch; + break; + case INSN_JSR: + info->insn_type = dis_jsr; + break; + case INSN_DREF: + info->insn_type = dis_dref; + break; + default: + break; + } + + if (op->pinfo & INSN_DATA_SIZE) + { + int size = ((op->pinfo & INSN_DATA_SIZE) + >> INSN_DATA_SIZE_SHIFT); + info->data_size = 1 << (size - 1); + } + return insnlen; } } |