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path: root/opcodes/riscv-dis.c
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* RISC-V: Cache the latest mapping symbol and its boundary.Kito Cheng2023-04-181-0/+43
* RISC-V: Allocate "various" operand typeTsukasa OI2023-03-311-5/+21
* RISC-V: Fix disassemble fetch fail return value.Jiawei2023-03-211-2/+2
* RISC-V: don't disassemble unrecognized insns as .byteJan Beulich2023-02-031-30/+20
* Update year range in copyright notice of binutils filesAlan Modra2023-01-011-1/+1
* RISC-V: Better support for long instructions (disassembler)Tsukasa OI2022-11-281-5/+9
* RISC-V: Output mapping symbols with ISA string.Nelson Chu2022-10-281-0/+9
* opcodes/riscv-dis.c: Remove last_map_stateTsukasa OI2022-10-141-3/+0
* opcodes/riscv-dis.c: Make XLEN variable staticTsukasa OI2022-10-141-1/+1
* opcodes/riscv-dis.c: Use bool type whenever possibleTsukasa OI2022-10-141-5/+5
* opcodes/riscv-dis.c: Tidying with spacingTsukasa OI2022-10-141-1/+1
* opcodes/riscv-dis.c: Tidying with comments/clarityTsukasa OI2022-10-141-4/+21
* RISC-V: Print XTheadMemPair literal as "immediate"Tsukasa OI2022-10-061-1/+1
* RISC-V: Fix T-Head immediate types on printingTsukasa OI2022-10-061-4/+4
* RISC-V: Print comma and tabs as the "text" styleTsukasa OI2022-10-061-11/+20
* RISC-V: Optimize riscv_disassemble_data printfTsukasa OI2022-10-061-6/+4
* RISC-V: Fix printf argument types corresponding %xTsukasa OI2022-10-061-7/+7
* RISC-V: Fix immediates to have "immediate" styleTsukasa OI2022-10-061-5/+5
* RISC-V: Fix buffer overflow on print_insn_riscvTsukasa OI2022-10-041-1/+1
* opcodes/riscv: style csr names as registersAndrew Burgess2022-10-041-1/+2
* RISC-V: fix build after "Add support for arbitrary immediate encoding formats"Jan Beulich2022-09-301-2/+2
* RISC-V: Add support for literal instruction argumentsChristoph Müllner2022-09-221-0/+9
* RISC-V: Add support for arbitrary immediate encoding formatsChristoph Müllner2022-09-221-0/+34
* RISC-V: Remove "b" operand type from disassemblerTsukasa OI2022-09-221-1/+0
* opcodes: Add non-enum disassembler optionsTsukasa OI2022-09-061-0/+2
* RISC-V: Print highest address (-1) on the disassemblerTsukasa OI2022-09-021-6/+14
* RISC-V: PR29342, Fix RV32 disassembler address computationTsukasa OI2022-09-021-1/+7
* RISC-V: Fix disassembling Zfinx with -M numericTsukasa OI2022-07-071-1/+1
* opcodes: don't assume ELF in riscv, csky, rl78, mep disassemblersThomas Hebb2022-04-301-16/+12
* opcodes/riscv: implement style support in the disassemblerAndrew Burgess2022-04-041-72/+121
* RISC-V: Prefetch hint instructions and operand setTsukasa OI2022-03-181-0/+4
* Update year range in copyright notice of binutils filesAlan Modra2022-01-021-1/+1
* RISC-V: The vtype immediate with more than the defined 8 bits are preserved.Nelson Chu2021-11-301-1/+1
* RISC-V: Dump vset[i]vli immediate as numbers once vsew or vlmul is reserved.Nelson Chu2021-11-301-1/+3
* opcodes/riscv: add disassembler options support to libopcodesAndrew Burgess2021-11-261-9/+138
* RISC-V: Add instructions and operand set for z[fdq]inxjiawei2021-11-181-0/+4
* RISC-V: Support rvv extension with released version 1.0.Nelson Chu2021-11-171-0/+67
* RISC-V: Scalar crypto instructions and operand set.jiawei2021-11-161-0/+8
* RISC-V: Dump objects according to the elf architecture attribute.Nelson Chu2021-11-111-6/+26
* RISC-V: Tidy riscv assembler and disassembler.Nelson Chu2021-10-271-8/+10
* riscv: print .2byte or .4byte before an unknown instruction encodingAndrew Burgess2021-09-201-1/+23
* RISC-V: Pretty print values formed with lui and addiw.Jim Wilson2021-09-081-5/+18
* RISC-V: PR28291, Fix the gdb fails that PR27916 caused.Nelson Chu2021-08-301-2/+2
* RISC-V: PR27916, Support mapping symbols.Nelson Chu2021-08-301-12/+233
* RISC-V: PR27814, Objdump crashes when disassembling a non-ELF RISC-V binary.Job Noorman2021-05-181-10/+14
* Use bool in opcodesAlan Modra2021-03-311-7/+7
* Remove bfd_stdint.hAlan Modra2021-03-311-1/+1
* RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.Nelson Chu2021-02-191-20/+17
* RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling.Nelson Chu2021-02-181-8/+13
* RISC-V: Error and warning messages tidy.Nelson Chu2021-01-151-1/+1
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