summaryrefslogtreecommitdiff
path: root/opcodes/i386-opc.tbl
Commit message (Expand)AuthorAgeFilesLines
* x86: FMA4 scalar insns ignore VEX.LJan Beulich2020-07-081-16/+16
* x86: Add SwapSourcesH.J. Lu2020-07-021-5/+5
* i386-opc.tbl: Add a blank lineH.J. Lu2020-06-261-0/+1
* x86: Correct VexSIB128 to VecSIB128H.J. Lu2020-06-261-27/+27
* x86: Rename VecSIB to SIB for Intel AMXH.J. Lu2020-06-261-78/+81
* x86: Correct xsusldtrk mnemonicH.J. Lu2020-06-141-1/+1
* Add support for intel TSXLDTRK instructions$Cui,Lili2020-04-071-0/+7
* Add support for intel SERIALIZE instructionLiliCui2020-04-021-0/+6
* x86: use template for AVX512 integer comparison insnsJan Beulich2020-03-091-48/+10
* x86: use template for XOP integer comparison, shift, and rotate insnsJan Beulich2020-03-091-100/+13
* x86: use template for AVX/AVX512 floating point comparison insnsJan Beulich2020-03-091-496/+22
* x86: use template for SSE floating point comparison insnsJan Beulich2020-03-091-64/+10
* x86: allow opcode templates to be templatedJan Beulich2020-03-091-90/+6
* x86: reduce amount of various VCVT* templatesJan Beulich2020-03-061-30/+20
* x86: drop/replace IgnoreSizeJan Beulich2020-03-061-699/+699
* x86: don't accept FI{LD,STP,STTP}LL in Intel syntax modeJan Beulich2020-03-061-3/+3
* x86: replace NoRex64 on VEX-encoded insnsJan Beulich2020-03-061-25/+25
* x86: drop Rex64 attributeJan Beulich2020-03-061-18/+18
* x86: add missing IgnoreSizeJan Beulich2020-03-061-18/+18
* x86: refine TPAUSE and UMWAITJan Beulich2020-03-061-4/+4
* x86: support VMGEXITJan Beulich2020-03-041-0/+1
* x86: Replace IgnoreSize/DefaultSize with MnemonicSizeH.J. Lu2020-03-031-0/+3
* x86: Allow integer conversion without suffix in AT&T syntaxH.J. Lu2020-03-031-10/+20
* x86: Remove CpuABM and add CpuPOPCNTH.J. Lu2020-02-171-3/+5
* x86: fold certain VCVT{,U}SI2S{S,D} templatesJan Beulich2020-02-171-21/+15
* x86: fold AddrPrefixOpReg templatesJan Beulich2020-02-171-24/+15
* x86/Intel: improve diagnostics for ambiguous VCVT* operandsJan Beulich2020-02-171-13/+23
* Remove Intel syntax comments on movsx and movzxH.J. Lu2020-02-141-3/+2
* x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZXJan Beulich2020-02-141-12/+5
* x86: correct VFPCLASSP{S,D} operand size handlingJan Beulich2020-02-121-2/+4
* x86: fold two JMP templatesJan Beulich2020-02-121-2/+1
* x86-64: Intel64 adjustments for insns dealing with far pointersJan Beulich2020-02-121-11/+16
* x86: drop ShortForm attributeJan Beulich2020-02-111-95/+95
* x86: drop stray ShortForm attributesJan Beulich2020-02-111-6/+6
* x86: Accept Intel64 only instruction by defaultH.J. Lu2020-02-101-11/+15
* x86-64: honor vendor specifics for near RETJan Beulich2020-01-301-2/+4
* x86: drop further pointless/bogus DefaultSizeJan Beulich2020-01-301-9/+9
* x86-64: Properly encode and decode movsxdH.J. Lu2020-01-271-1/+3
* x86: improve handling of insns with ambiguous operand sizesJan Beulich2020-01-211-1/+1
* x86: VCVTNEPS2BF16{X,Y} should permit broadcastingJan Beulich2020-01-211-2/+2
* x86: Add {vex} pseudo prefixH.J. Lu2020-01-171-0/+1
* x86: drop stale Vec_Imm4 related commentJan Beulich2020-01-161-2/+0
* x86: add a few more missing VexWIGJan Beulich2020-01-161-4/+4
* x86: VPEXTRQ/VPINSRQ are unavailable outside of 64-bit modeJan Beulich2020-01-161-8/+8
* x86: SYSENTER/SYSEXIT are unavailable in 64-bit mode on AMDJan Beulich2020-01-091-2/+4
* Update year range in copyright notice of binutils filesAlan Modra2020-01-011-1/+1
* x86: consolidate Disp<NN> handling a littleJan Beulich2019-12-271-18/+15
* x86-64: accept 64-bit LFS/LGS/LSS forms with suffix or operand size specifierJan Beulich2019-12-041-3/+3
* x86: drop some stray/bogus DefaultSizeJan Beulich2019-12-041-5/+5
* x86: drop redundant SYSCALL/SYSRET templatesJan Beulich2019-11-141-2/+0
View Lorry Controller Status