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* x86: various XOP insns lack L and/or W bit decodingJan Beulich2020-07-082-123/+630
* x86: FMA4 scalar insns ignore VEX.LJan Beulich2020-07-084-101/+58
* x86: re-work operand swapping for XOP shift/rotate insnsJan Beulich2020-07-082-74/+32
* x86: re-work operand handling for 5-operand XOP insnsJan Beulich2020-07-082-194/+19
* x86: re-work operand swapping for FMA4 and 4-operand XOP insnsJan Beulich2020-07-082-65/+49
* arc: Update vector instructions.Claudiu Zissulescu2020-07-073-77/+103
* x86: introduce %BW to avoid going through vex_w_table[]Jan Beulich2020-07-074-77/+27
* x86: adjust/correct VFRCZ{P,S}{S,D} decodingJan Beulich2020-07-062-12/+48
* x86: use %LW / %XW instead of going through vex_w_table[]Jan Beulich2020-07-064-192/+77
* x86: most VBROADCAST{F,I}{32,64}x* only accept memory operandsJan Beulich2020-07-065-24/+90
* x86: adjust/correct V*{F,I}{32x8,64x4}Jan Beulich2020-07-062-14/+22
* x86: drop EVEX table entries that can be made served by VEX onesJan Beulich2020-07-065-165/+92
* x86: AVX512 VPERM{D,Q,PS,PD} insns need to honor EVEX.L'LJan Beulich2020-07-065-4/+47
* x86: AVX512 extract/insert insns need to honor EVEX.L'LJan Beulich2020-07-065-9/+76
* x86: honor VEX.W for VCVT{PH2PS,PS2PH}Jan Beulich2020-07-065-15/+27
* x86: drop EVEX table entries that can be served by VEX onesJan Beulich2020-07-065-713/+185
* x86: replace EXqScalarS by EXqVexScalarSJan Beulich2020-07-063-3/+8
* x86: replace EX{d,q}Scalar by EXxmm_m{d,q}Jan Beulich2020-07-063-47/+48
* Fix spelling mistakes in some of the binutils sub-directories.Nick Clifton2020-07-063-3/+9
* Updated translations for various binutils sub-directoriesNick Clifton2020-07-063-603/+634
* Update version to 2.35.50 and regenerate filesNick Clifton2020-07-043-122/+127
* Add markers for binutils 2.35 branchNick Clifton2020-07-041-0/+4
* x86: Add SwapSourcesH.J. Lu2020-07-025-3987/+4001
* RISC-V: Support debug and float CSR as the unprivileged ones.Nelson Chu2020-06-302-3/+11
* C++ commentsAlan Modra2020-06-298-10/+19
* i386-opc.tbl: Add a blank lineH.J. Lu2020-06-262-0/+5
* x86: Correct VexSIB128 to VecSIB128H.J. Lu2020-06-262-29/+29
* x86: Rename VecSIB to SIB for Intel AMXH.J. Lu2020-06-264-85/+106
* x86: make I disassembler macro available for new useJan Beulich2020-06-262-13/+17
* x86: fix processing of -M disassembler optionJan Beulich2020-06-262-3/+8
* x86: make J disassembler macro available for new useJan Beulich2020-06-252-12/+13
* x86: drop left-over 4-way alternative disassembler templatesJan Beulich2020-06-252-2/+6
* x86: fix SYSRET disassembly, improve {,V}CVTSI2S{S,D} and PTWRITEJan Beulich2020-06-252-6/+14
* RISC-V: Report warning when linking the objects with different priv specs.Nelson Chu2020-06-223-50/+6
* x86: also test alternative VMGEXIT encodingJan Beulich2020-06-182-0/+6
* x86: Delete incorrect vmgexit entry in prefix_tableCui,Lili2020-06-172-2/+4
* x86: Correct xsusldtrk mnemonicH.J. Lu2020-06-144-3/+10
* RISC-V: Drop the privileged spec v1.9 support.Nelson Chu2020-06-122-1/+4
* [PATCH]: aarch64: Refactor representation of system registersAlex Coplan2020-06-112-623/+471
* i386-dis.c: Fix a typo in commentsH.J. Lu2020-06-092-1/+5
* x86: consistently print prefixes explicitly which are invalid with VEX etcJan Beulich2020-06-092-13/+11
* x86: fix {,V}MOV{L,H}PD disassemblyJan Beulich2020-06-092-23/+48
* x86: utilize X macro in EVEX decodingJan Beulich2020-06-096-411/+127
* x86: correct decoding of packed-FP-only AVX encodingsJan Beulich2020-06-092-31/+39
* x86: correct mis-named MOD_0F51 enumeratorJan Beulich2020-06-092-3/+8
* [PATCH] arm: Add DFB instruction for ARMv8-RAlex Coplan2020-06-082-0/+13
* x86: restrict use of register aliasesJan Beulich2020-06-082-1/+5
* Power10 tidiesAlan Modra2020-06-062-0/+9
* bpf stack smashing detectedAlan Modra2020-06-052-5/+11
* cpu,gas,opcodes: remove no longer needed workaround from the BPF portJose E. Marchesi2020-06-045-27/+35
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